Staff RTL Design Engineer - Cache Subsystem (RISC-V)

Location: Hsinchu, Taiwan; right to work in Taiwan required.

Company

hirify.global develops high-performance compute platforms and CPU core generators based on the open-source RISC-V architecture for applications including artificial intelligence, machine learning, automotive, data center, mobile, and consumer markets.

What you will do

• Architect, design, and implement high-performance cache subsystems in RISC-V CPU core generators.
• Enhance features and performance in existing cache subsystems.
• Develop and specify microarchitecture while documenting designs and sharing knowledge.
• Perform initial sandbox verification and create and execute detailed verification test plans with the verification team.
• Work with physical implementation engineers to optimize frequency, area, and power.
• Collaborate with performance modelling engineers on performance exploration and optimization.

Requirements

• At least five years of relevant industry experience designing high-performance, energy-efficient cache subsystems, ideally within a CPU or GPU subsystem.
• Successful cache subsystem development experience from architecture through tapeout.
• Expertise in multi-level coherent cache architectures and designs.
• Experience with TileLink or a similar interconnect architecture.
• Proficiency in RTL hardware design using Verilog, SystemVerilog, or VHDL.
• Attention to detail and focus on high-quality design.
• Ability to collaborate effectively and work as part of an engineering team.
• Bachelor’s or Master’s degree in EE, CE, CS, or a related technical discipline, or equivalent experience.

Nice to have

• Knowledge of RISC-V architecture.
• Experience with Scala and/or Chisel.
• Understanding of IP verification tools and methodologies such as UVM and Formal.
• Knowledge of at least one object-oriented and/or functional programming language.

Culture & Benefits

• Collaborative engineering culture focused on knowledge sharing and teamwork.
• Fast-paced environment developing innovative hardware IP.
• Employment is contingent on successful background and reference checks.
• Employment is contingent on authorization to access export-controlled technology or hirify.global obtaining the required export licenses or approvals.
• Inclusive equal-opportunity workplace committed to diversity.