Senior IC Packaging Engineer (AI Semiconductor)

Location: Taipei, Taiwan

Company

hirify.global is a fast-growing semiconductor startup building AI-driven Trusted Control/Compute Units and secure, efficient infrastructure hardware.

What you will do

• Serve as the technical authority for IC and System-in-Package packaging across multiple products and programs.
• Own package architectures and technology roadmaps covering 2D, RDL-based fan-out, 2.5D, chiplet, and heterogeneous integration designs.
• Lead chiplet packaging strategies involving UCIe, silicon interposers, advanced RDL, substrate stack-ups, materials, bumps, and DFM guidelines.
• Perform and guide package design and physical layout for high-speed SerDes/PHY, PCIe, CXL, LPDDR5, UCIe, and other multi-gigabit interfaces.
• Drive signal-integrity, power-integrity, thermal, mechanical, reliability, cost, yield, schedule, and risk trade-offs.
• Lead collaboration with OSATs, foundries, substrate suppliers, and internal design, product, test, operations, reliability, and customer teams from technology development through production ramp.

Requirements

• BSEE or MSEE in Electrical Engineering or a related field; PhD is a plus.
• 10+ years of extensive IC packaging experience for SoCs, ASICs, or memory products.
• Deep hands-on expertise in Flip-Chip BGA, System-in-Package, RDL, silicon interposers, and chiplet architectures including UCIe.
• Technical leadership of multiple end-to-end packaging programs from early architecture through high-volume production.
• Experience with high-speed SerDes package development, including PCIe Gen5, LPDDR5/LPDDR5X, USB 3.x, or 10G interfaces.
• Experience defining die-to-die and chiplet-based RDL and bump architectures.
• Direct collaboration with OSATs, foundries, and substrate suppliers for co-development and ramp.
• Strong cross-functional leadership and understanding of electrical, mechanical, thermal, reliability, cost, yield, schedule, and risk trade-offs.
• Ability to operate autonomously, make high-impact decisions, and execute in a startup environment.

Nice to have

• PhD in Electrical Engineering or a related field.
• Experience with Cadence Allegro Package Designer or equivalent EDA tools.
• SI/PI expertise, including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer.
• Experience building new packaging methodologies or platforms from scratch.

Culture & Benefits

• Fast-growing, well-funded startup environment with high-impact and high-ambiguity work.
• Every employee holds equity in the company.
• Culture emphasizes persistence, curiosity, continuous learning, hard and smart work, and mutual support.
• Diverse and multifaceted working environment with a focus on solving real-world infrastructure and security problems.