Staff EMIB-T Substrate Yield Engineer (Advanced Packaging)

Location: Taipei or Hsinchu, Taiwan; hybrid work model with regular on-site work at the assigned hirify.global site

Company

hirify.global develops semiconductor technologies and advanced packaging platforms for heterogeneous integration.

What you will do

• Own daily yield performance and technical issue closure for assigned supplier lines, modules, products, or process areas.
• Lead investigations from containment and hypothesis development through experiments, failure analysis, corrective action, and sustainment.
• Use statistical and spatial analytics to identify defect and yield signatures across lines, tools, materials, panel positions, geometries, products, and time.
• Define supplier actions, owners, completion criteria, control limits, and verification plans.
• Support DFM/DFY, qualification, ramp readiness, change control, and deployment of dashboards or automated analytics.
• Document reusable learning and communicate facts, hypotheses, decisions, and residual risks.

Requirements

• Master’s degree with 4+ years of experience or PhD with 2+ years of experience in engineering, materials science, physics, chemistry, data science, or a related technical discipline.
• 4+ years of experience in semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, process engineering, or a closely related field.
• Hands-on experience with statistical analysis, defect reduction, process optimization, SPC, DFM/DFY, defect metrology, failure analysis, and high-volume manufacturing execution.
• Experience influencing cross-functional organizations and suppliers while independently driving complex technical issues to closure.
• Experience with yield monitoring systems, automated analytics, dashboards, image analytics, computer vision, AI/ML-based defect detection, or automated defect classification.
• Professional proficiency in Mandarin and English for technical work is required.

Nice to have

• Experience working directly with substrate suppliers and external manufacturing partners.
• Program leadership experience coordinating cross-functional technical teams in high-visibility environments.
• Experience with semi-additive processing, build-up films, micro vias, copper plating, lithography, lamination, embedded silicon, TSV, 2.5D/3D packaging, or heterogeneous integration.
• Experience supporting technology development, qualification, and manufacturing ramp of advanced semiconductor technologies.

Culture & Benefits

• Hybrid work model combining on-site work at the assigned hirify.global site with off-site work.
• Work supports next-generation EMIB-T advanced packaging technologies across Taiwan suppliers.
• High-visibility, high-accountability environment spanning hirify.global Foundry Services and hirify.global Product Groups.
• Shift 1 schedule in Taiwan.