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4 дня назад

Principal IC Package Design Engineer (Ethernet)

200 000 - 265 000$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Principal IC Package Design Engineer (Ethernet): Designing and delivering advanced packages for next-generation Ethernet switches and PHYs with an accent on package architecture, high-speed multilayer layouts, and SI/PI and thermal co-design. Focus on optimizing FCBGA, FCCSP, SiP, and MCM designs, integrating substrate and manufacturing constraints, and driving OSAT and vendor execution from feasibility through production.

Location: San Jose, CA; hybrid work arrangement.

Annual base salary: $200,000–$265,000, plus pre-IPO ISO options and benefits.

Company

hirify.global develops Ethernet-based networking and acceleration technology for software-defined and autonomous vehicles, robotics, and other intelligent machines.

What you will do

  • Lead package architecture and feasibility, including package concepts, substrate stack-ups, bump and ball maps, and pinouts optimized for cost, electrical performance, and thermal constraints.
  • Design complex, high-speed, multilayer FCBGA, FCCSP, and SiP packages using industry-standard EDA tools.
  • Perform SI/PI and thermal co-design for 56G/112G+ SerDes, power delivery networks, and thermal dissipation.
  • Define substrate design rules, optimize routing, and manage DFM/DFA and manufacturing constraints.
  • Lead technical engagements with substrate suppliers and OSAT vendors through NPI and production ramp.
  • Coordinate chip-package-board co-design across Silicon IC Design, Systems/PCB, Reliability, Thermal, and external partners while influencing the packaging technology roadmap.

Requirements

  • B.S. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
  • 10+ years of direct experience in IC package design and architecture, ideally in high-speed networking, automotive electronics, or high-performance computing.
  • Proven experience delivering high-volume, complex FCBGA, SiP, and MCM designs.
  • Expert proficiency with package design suites such as Cadence Allegro Package Designer, SiP Layout, or Synopsys 3DIC Compiler.
  • Strong understanding of electromagnetic theory, transmission lines, crosstalk, and PDN concepts.
  • Deep knowledge of substrate fabrication processes, assembly line limits, and automotive-grade reliability standards such as AEC-Q100 guidelines.
  • Strong problem-solving abilities with a data-driven approach to architectural trade-offs involving performance, cost, and yield.
  • Excellent communication skills for explaining complex packaging constraints to cross-functional executives and external partners.

Nice to have

  • Familiarity with extraction tools such as Ansys HFSS/Q3D or Cadence Clarity.
  • Experience in high-speed networking, automotive electronics, or high-performance computing.

Culture & Benefits

  • Opportunity to work on cutting-edge packaging and networking technology in a growing startup.
  • Career growth opportunities and exposure to broad technology areas.
  • Pre-IPO stock options.
  • Flexible hours.
  • Medical, dental, and vision insurance for employees.
  • Competitive base salary and incentive compensation.

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