обновлено 4 дня назад
Package Design Engineer (AI)
121 900 - 195 000$
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Package Design Engineer (AI): Designing complex flip-chip-BGA packages for high-performance ASICs supporting AI, networking, HPC, and 5G applications with an accent on signal integrity, power integrity, thermal performance, reliability, and manufacturability. Focus on physical package layout, high-speed SerDes and memory structures, coordinating multiple projects, and improving design processes through automation and documentation.
Location: San Jose, California, USA. On-site at the office 5 days per week; this is not a remote-work position.
Salary: USD 121,900–195,000 annual base salary, plus discretionary annual bonus and equity awards.
Company
develops semiconductor and infrastructure technology, including high-performance ASICs for AI, networking, high-performance computing, and 5G applications.
What you will do
- Own the design of complex flip-chip-BGA packages for high-performance ASICs.
- Design critical package structures for 224G-and-higher SerDes, ADC/DAC, DDR, HBM, and related technologies.
- Address signal integrity, power integrity, manufacturability, reliability, and thermal requirements.
- Perform physical package design and layout as a foundational responsibility.
- Schedule, prioritize, and track work across two or more projects while managing customer interfaces.
- Improve design-team efficiency through process development, automation, and documentation.
Requirements
- BSEE or a similar degree with 8+ years of flip-chip-BGA package-design experience, including high-speed SerDes, or an MSEE or similar degree with 6+ years of experience.
- Knowledge of package-level signal integrity and power integrity.
- Experience with Cadence APD, Allegro Package Designer, or an equivalent tool.
- Ability to collaborate with worldwide teams across multiple time zones, including internal engineers and external vendor designers.
- Strong self-management and organizational skills.
- Availability to work on-site at the San Jose office five days per week.
Nice to have
- One or more years of experience with Cadence SKILL for Allegro or similar design-automation coding.
- Interest in design automation and process improvement.
Culture & Benefits
- Collaboration within a worldwide R&D team.
- Medical, dental, and vision plans.
- 401(k) participation with company matching and an Employee Stock Purchase Program.
- Paid holidays, sick leave, vacation, family leave, and other applicable leaves of absence.
- Eligibility for discretionary bonuses and new-hire and annual equity awards.
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