Package Design Engineer (AI)

TL;DR

Package Design Engineer (AI/ASIC): Designing complex flip-chip-BGA packages for high-performance ASICs used in AI, networking, and 5G with an accent on signal integrity, power integrity, and high-speed SerDes. Focus on physical layout design, thermal reliability, and automation of design processes using Cadence tools.

Location: On-site in San Jose, CA (5 days a week)

Salary: $121,900 – $195,000

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Own the overall design of ASIC packages, ensuring signal integrity (SI), power integrity (PI), and thermal reliability.
• Design critical structures for SerDes (224G+), ADC/DAC, DDR, and HBM.
• Perform physical layout for flip-chip BGA packages as a foundational responsibility.
• Manage multiple design projects simultaneously and interface with customers.
• Improve design team efficiency through automation, process development, and documentation.

Requirements

• BSEE with 8+ years or MSEE with 6+ years of experience in flip-chip-BGA package design.
• Proven expertise in high-speed SerDes.
• Strong knowledge of package-level signal integrity and power integrity.
• Experience with Cadence APD (Allegro Package Designer) or equivalent tools.
• Must be able to work on-site in San Jose, CA, 5 days a week.

Nice to have

• 1+ years of experience with Cadence SKILL for Allegro or similar design-automation coding.

Culture & Benefits

• Comprehensive medical, dental, and vision plans.
• 401(K) with company matching and Employee Stock Purchase Program (ESPP).
• Annual discretionary bonus and equity grants.
• Paid sick leave, vacation, and company-paid holidays.