Staff / Principal RTL Design Engineer (LLM Inference ASICs)

Location: South Bay, around Palo Alto / Menlo Park; full-time in office

Salary: $150,000–$220,000 base annually

Company

hirify.global is hiring for a seed-funded AI hardware startup building a dedicated LLM inference chip and its surrounding software stack.

What you will do

• Translate microarchitecture into synthesizable RTL and own a substantial design scope.
• Design and debug datapaths, control logic, and block interfaces.
• Collaborate with verification and physical-design engineers to resolve correctness issues.
• Address implementation constraints and prepare designs for tapeout readiness.

Requirements

• Staff, Senior Staff, or Principal-level engineering experience.
• Hands-on delivery of substantial ASIC or SoC RTL designs.
• Strong Verilog or SystemVerilog skills.
• Ability to explain difficult logic problems solved in previous projects.
• Must work full-time from the office in the South Bay, around Palo Alto or Menlo Park.

Nice to have

• AI accelerator or inference ASIC experience.
• Strong adjacent digital-silicon experience.

Culture & Benefits

• Work closely with a founding team combining Stanford AI research and silicon experience from NVIDIA, Groq, and Google’s TPU team.
• Stay close to detailed engineering while shaping a new inference platform.
• Join an early hardware team at a startup with tens of millions raised.