SoC Design Verification Engineer

Location: Santa Clara, California, United States; hybrid work model with time split between the hirify.global site and off-site.

Annual salary: $105,650–$149,150 USD.

Company

hirify.global develops semiconductor and computing technologies across areas including server products, AI, analytics, and cloud-to-edge technology.

What you will do

• Perform functional logic verification and emulation validation of integrated SoCs to confirm compliance with specifications.
• Develop reusable block, subsystem, and SoC verification plans, test benches, and verification environments.
• Execute emulation and system simulations to analyze power and performance, identify bugs, and validate designs.
• Replicate, root-cause, debug, and resolve pre-silicon test failures.
• Collaborate with SoC architects, micro-architects, full-chip architects, RTL developers, post-silicon, and physical design teams.
• Document technical plans and reviews, execute security coverage activities, maintain verification infrastructure, and incorporate post-silicon learning into future validation plans.

Requirements

• Master's degree in electrical engineering, computer science, engineering, or a related field.
• At least 10 months of experience with silicon design and/or validation/verification.
• At least 10 months of experience with x86 architecture.
• At least 10 months of design and validation experience across global domains including reset, clock, fuse, GPIO, and MPP.
• Self-reliance in taking issues to closure, ownership of assigned tasks, problem-solving ability, strong communication, quick learning, teamwork, and openness to learning and teaching validation techniques.

Nice to have

• Experience developing, maintaining, and executing complex IPs and/or SoCs for design or design verification.
• Strong debugging skills and understanding of cache coherency in multiprocessor SoCs.
• Experience with layered protocols including transaction, data link, and PHY layers.
• Experience with UVM/SystemVerilog constrained-random, coverage-based design verification, and formal verification methodology.
• Experience across the full verification lifecycle, including architecture, test planning, execution, debugging, and coverage closure.
• Experience developing validation test suites and improving existing validation methodologies.
• Xeon CPU pre-silicon, emulation, or post-silicon validation experience.
• Knowledge of one or more scripting languages for automation.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Health, retirement, vacation, and other employee benefits.
• Competitive compensation with stock bonuses.
• Equal employment opportunity and ethical hiring practices.