2 дня назад
Design Verification Manager (Mixed-Signal IC)
116 000 - 216 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Design Verification Manager (Mixed-Signal IC): Leading verification teams and developing comprehensive verification strategies for mixed-signal integrated circuit blocks and systems with an accent on SystemVerilog, UVM, coverage closure, and RTL, gate-level, and AMS verification. Focus on managing complex testbenches, scaling reusable verification environments, driving continuous integration and regression testing, and coordinating silicon validation with cross-functional engineering teams.
Location: San Diego, CA or San Jose, CA — hybrid, with Fridays remote
Base salary: USD $116,000–$216,000 per year
Company
supplies analog and mixed-signal semiconductors for consumer, computing, communications, industrial, and automotive applications.
What you will do
- Lead, mentor, and develop geographically distributed design verification engineers across multiple projects.
- Define verification strategies, test plans, coverage models, and verification environments for digital and mixed-signal IC blocks and systems.
- Manage SystemVerilog and UVM testbench development, including RTL, gate-level, and AMS verification.
- Drive functional, code, and assertion-based coverage closure, regression testing, continuous integration, scoreboards, monitors, and checkers.
- Track verification progress, report quantitative metrics, and identify and mitigate project risks.
- Collaborate with system, digital hardware, firmware, analog, silicon validation, test, product, and application engineering teams.
Requirements
- 10+ years of industry experience in integrated circuit design verification.
- B.S. or M.S. degree in Electrical or Computer Engineering.
- Experience leading, mentoring, or managing engineers or projects.
- In-depth experience verifying MCU-based digital IC systems, including ARM, RISC-V, PIC, or STM32 architectures, memories, interfaces, peripherals, and external IP.
- Proficiency in SystemVerilog, UVM, Verilog or VHDL, Python or Perl, debugging, and industry-standard EDA verification tools from Synopsys, Siemens, or Cadence.
- Strong analytical, problem-solving, technical leadership, communication, and follow-through skills.
Nice to have
- Knowledge of signal processing, mixed-signal systems, digital hardware, embedded firmware, analog modeling, testing, and applications.
- Experience with I2C, I3C, SPI, or MIPI protocols.
- Experience with mixed-signal products, AMS verification, and analog behavioral modeling using SV RNM, Verilog, or VHDL.
- Experience developing circuits for consumer or industrial, telecommunications, and automotive markets.
Culture & Benefits
- Hybrid work arrangement with remote work on Fridays.
- Collaboration across geographically distributed engineering teams.
- Opportunities to introduce advanced verification methodologies, best practices, and tools.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
9 дней назад
Design Verification Engineer (AI Networking)
120 000 - 192 000$
7 дней назад
Pre-Silicon Verification Engineer (SystemVerilog/UVM)
122 440 - 172 860$
9 дней назад
ASIC Design Verification Engineer (SystemVerilog/UVM)
129 400 - 207 000$
8 дней назад
Senior Design Verification Engineer (Emulation)
153 500 - 310 500$
9 дней назад
Lead ASIC Design Engineer (Digital Design)
143 800 - 230 000$
2 дня назад