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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior Design Verification Engineer (FPGA/ASIC): Leading functional verification of complex FPGA/ASIC IPs, subsystems, and SoC features from specification through tape-out with an accent on SystemVerilog/UVM environments, coverage closure, and cross-level debugging. Focus on architecting scalable verification infrastructure, driving constrained-random and directed testing, resolving RTL and system-level issues, and supporting silicon bring-up.
Location: Penang, Malaysia. The role requires satisfactory proof of the right to work in Malaysia.
Company
hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.
What you will do
Lead verification of complex FPGA/ASIC IPs, subsystems, and SoC features from specification through tape-out.
Develop verification strategies, test plans, and closure criteria aligned with product requirements.
Architect scalable SystemVerilog/UVM environments with drivers, monitors, checkers, assertions, scoreboards, and coverage models.
Drive constrained-random and directed verification, regression analysis, coverage closure, sign-off, and risk assessment.
Debug RTL, gate-level, low-power, system-level, testbench, simulation, and integration issues.
Collaborate with architects, design, firmware, and validation engineers; support silicon bring-up, root-cause analysis, mentoring, and methodology improvements.
Requirements
Bachelor’s or Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.
5+ years of experience in ASIC/FPGA functional verification.
Strong expertise in SystemVerilog and UVM.
Experience developing verification environments with drivers, monitors, scoreboards, assertions, and coverage models.
Strong debugging skills across RTL, gate-level, and system-level simulations.
Experience with industry-standard simulators and verification tools.
Strong scripting skills in Python, Perl, Shell, or an equivalent scripting language.
Nice to have
Experience with PCIe, USB, MIPI CSI/DSI, Ethernet, SerDes, or other high-speed protocols.
Experience with low-power verification methodologies such as UPF/CPF.
Experience with GLS, timing analysis, and post-silicon debugging.
Knowledge of FPGA architecture and programmable logic devices.
Previous experience leading verification activities for a major IP or subsystem.
Experience mentoring engineers and driving methodology improvements.
Culture & Benefits
Work in a fast-paced, results-oriented, team-first environment.
Collaborate within an international organization focused on R&D, product innovation, and customer service.
Comprehensive compensation and benefits programs are provided.
A diverse workplace welcomes qualified candidates and values different ideas, perspectives, and experiences.
Hiring process
Successful background and reference checks are required.
Satisfactory proof of the right to work in Malaysia is required.
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