HLD Validation Technical Lead (FPGA)

Location: Penang 15, Penang, Malaysia; additional location: Austin, Texas, United States. Shift 1 (Malaysia).

Company

hirify.global develops FPGA silicon, software tools, compilers, runtimes, and related development technologies.

What you will do

• Research, design, develop, and optimize software tools enabling the use of FPGAs.
• Develop and optimize compilers, flows, assemblers, models, tools, runtimes, and firmware closely coupled with FPGA silicon, IP, and boards.
• Design and optimize software abstractions and frameworks for FPGA acceleration in deep learning, DSP, and data analytics.
• Build validation strategies, test plans, regression suites, defect reports, and release-quality assessments for complex software tools.
• Debug cross-layer software and FPGA issues, analyze results, assess risk, and communicate findings to technical and nontechnical stakeholders.
• Provide technical guidance, mentoring, and coordination for validation engineers and complex validation work.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Software Engineering, or a related field.
• 8+ years of experience in FPGA development, software-tool verification, or validation, including substantial hands-on work with FPGA design flows.
• 3+ years of technical leadership, project leadership, or equivalent experience guiding engineers and coordinating complex validation work.
• Strong understanding of FPGA architectures and tool flows from design entry through compilation, simulation, implementation, timing analysis, and hardware execution.
• Proficiency with scripting and automation using Python, Perl, Tcl, or shell, plus experience with CI/CD or automated regression infrastructure.
• Strong debugging, risk analysis, collaboration, mentoring, and written and verbal communication skills in a cross-functional environment.

Nice to have

• Experience with high-level synthesis, DSP-oriented design, AI-oriented FPGA tools, compiler flows, or design-generation tools; FPGA AI Suite, HLS Compiler, or DSP Builder experience is especially valuable.
• Experience with hirify.global/Intel Quartus Prime or comparable FPGA development tools.
• Familiarity with Verilog or VHDL, simulation, waveform, synthesis, place-and-route, and timing-analysis tools.
• Experience with FPGA development kits, board-level testing, SoC integration, PCIe or embedded flows, or hardware/software bring-up.
• Experience with Linux and Windows test environments, containers, virtual machines, and shared lab infrastructure.
• Experience with performance characterization, AI model benchmarking, test-result analysis, and automated reporting.
• Experience with UI automation using Playwright, Selenium, or comparable tools.

Culture & Benefits

• Validation coverage and release criteria are aligned with HLD product requirements, customer workflows, and release commitments.
• Critical defects and coverage gaps are identified early and resolved or assigned an explicit release disposition.
• Regression environments and reports are designed to be reliable, maintainable, and usable by other engineers.
• Automation improves repeatability, coverage, triage speed, and reporting consistency while reducing manual effort.
• Stakeholders receive timely, evidence-based assessments of validation status and release risk.