Назад
Company hidden
9 дней назад

Senior Design Verification Engineer

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Philippines
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Senior Design Verification Engineer (SystemVerilog/UVM): Developing verification plans, testbenches, regression environments, and coverage models for digital design blocks, subsystems, and full-chip SoC verification with an accent on assertion-based, formal, directed, and randomized testing. Focus on building UVM components and verification tools, debugging complex digital designs, and delivering reliable verification results on aggressive schedules.

Location: Manila, Philippines. Successful background and reference checks and satisfactory proof of the right to work in the Philippines are required.

Company

Develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices, with an international engineering and operations organization.

What you will do

  • Develop comprehensive verification plans, define clear metrics, and track progress throughout the project.
  • Verify design blocks, subsystems, and full-chip SoC designs using assertion-based verification, formal verification, directed tests, and randomized tests.
  • Develop SystemVerilog and C-based testbenches in a UVM environment, including Universal Verification Components, BFMs, and verification tools.
  • Design verification regression environments and perform functional, RTL code, assertion, and gate-level coverage and simulations.
  • Collaborate with design engineers, IP developers, and software developers to deliver high-quality SoC verification on aggressive schedules.
  • Develop best practices and methods for SoC verification.

Requirements

  • 6–10 years of digital design verification-related experience.
  • Bachelor’s or master’s degree in Computer Science, Computer Engineering, Electronics Engineering, or Electrical Engineering.
  • Skill in debugging and analyzing complex digital designs.
  • Experience with HDL and HVL languages and methodologies.
  • Experience with ASIC, FPGA, or SoC verification or development cycles.
  • Experience with simulation tools such as Cadence IES/XCELIUM, Synopsys VCS, or Mentor Questa.
  • Hands-on experience with Python, Perl or Shell scripting, TCL, and Make.
  • Strong communication, analytical, and documentation skills, with the ability to interface with other groups and sites.
  • Ability to stay up to date with industry trends and verification technology development.

Culture & Benefits

  • Fast-paced, results-oriented environment with a team-first and collegial working culture.
  • Opportunities to contribute, learn, and grow within a dynamic Silicon team.
  • Comprehensive compensation and benefits program.
  • Inclusive workplace that values diverse individuals, ideas, perspectives, insights, and values.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →