aipythonsignal integritypcb designserdeshfsselectromagneticssigrityhigh speed digital design
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Выше рынка
$150к-250к/год
$110к$140кмедиана$160к
По похожим ролям (50) ~ $140к/год
На СНГ рынке: $1.4к/мес ($1.1к - $1.8к)
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Крутая вакансия
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Чётко очерченная инженерная роль в финансируемой AI-компании предлагает зарплату выше рыночного ориентира. Основные компромиссы - работа в офисе и поездки до 25% времени.
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КомандировкиВыше рынкаAI для hardwareСильное финансированиеЧёткие задачи
Оценка от Hirify AI
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Electrical Engineer (SerDes and Signal Integrity) (AI/hardware simulation): Building and validating high-speed SerDes channel simulation capabilities for Atlas, spanning PCB traces, vias, connectors, packages, and cables, with an accent on signal integrity analysis, electromagnetic simulation, and lab correlation. Focus on developing production-grade 2.5D/3D EM workflows, optimizing PAM4 links at 112G and 224G, and automating simulation pipelines against VNA, TDR, and BER measurements.
Location: Work in person at the New York City headquarters; domestic and international travel required for up to 25% of the time. Relocation support is provided.
Base salary: $150,000–$250,000 per year, plus equity and benefits.
Company
Builds Atlas, an AI platform that applies physics-grounded intelligence to verify, debug, and optimize hardware across its lifecycle.
What you will do
Model SerDes channels end to end, including PCBs, vias, connectors, packages, and cables.
Generate S-parameters, RLGC extractions, and channel operating margin estimates for high-speed PAM4 links.
Characterize insertion and return loss, crosstalk, impedance discontinuities, skew, mode conversion, resonance, and material losses.
Develop production-grade 2.5D and 3D electromagnetic simulation workflows for SerDes structures.
Correlate simulations with VNA, TDR, and BER measurements and lead root-cause analysis for discrepancies.
Automate parameterized SerDes simulation and post-processing workflows, while integrating PCB design expertise into Atlas.
Requirements
3+ years of industry experience in signal integrity, SerDes channel engineering, or high-speed digital design at a hardware or semiconductor company.
Strong knowledge of signal integrity fundamentals, including loss, crosstalk, impedance discontinuities, via stubs, backdrilling, skew, mode conversion, and de-embedding.
Practical experience with 2.5D/3D EM solvers such as Ansys HFSS/SIwave, Keysight ADS/Momentum, or Cadence Sigrity/Clarity.
Knowledge of 112G/224G PAM4, PCIe Gen5/6, IBIS-AMI models, eye-diagram optimization, and BER budgeting.
Experience with VNA, TDR, and BERT equipment, test planning, and simulation-to-measurement correlation.
PCB design experience with Altium or Cadence OrCAD/Allegro, plus Python scripting for simulation pipelines.
Nice to have
PhD in Electrical Engineering, Applied Physics, or a related field.
Experience with low-loss laminate systems and high-volume PCB manufacturing constraints.
Experience debugging EMI/EMC de-sense issues on high-speed digital boards.
Culture & Benefits
Medical, vision, and dental insurance premiums fully covered for employees and dependents.
401(k) retirement plan.
Unlimited paid time off.
Daily lunch from local restaurants.
Relocation support.
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