physical designasicsoclow power designedatclstatic timing analysissynthesisplace and route
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Очень мало
$112к-165к/год
$150к$190кмедиана$220к
По похожим ролям (50) ~ $190к/год
На СНГ рынке: $1.9к/мес ($1.8к - $3к)
58
Средняя вакансия
развернуть
Роль описана достаточно четко и дает опыт в ASIC, но зарплата заметно ниже ориентира для похожих senior-позиций, а работа полностью офисная и предполагает поездки к клиентам.
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Ниже рынкаАктуальная специализацияЧеткие задачиОфис и поездки
Оценка от Hirify AI
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Physical Design Engineer (ASIC): Executing synthesis, place and route, static timing analysis, and signoff for ASIC partitions with an accent on sub-7nm SoC implementation, low-power design, and physical verification. Focus on closing EM/IR, driving LEC convergence, developing TCL-based EDA flows, and resolving implementation issues with design teams and EDA vendors.
Location: Complete on-site at San Jose, California; must be able to travel to an Arrow client office location as requested by client leadership.
Annual hiring range: $112,200–$165,000.
Company
eInfochips, an hirify.global company, provides product engineering and semiconductor design services, including ASIC and connected-product development across multiple industries.
What you will do
Execute synthesis, place and route, and static timing analysis for assigned ASIC chip partitions.
Collaborate with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues.
Close electromigration and IR issues and drive logical equivalence checking and physical verification signoff.
Identify physical design challenges and support efficient design iteration and convergence.
Refine synthesis, place-and-route, EM/IR, power delivery network, and logical equivalence checking methodologies.
Troubleshoot implementation flow issues and work with EDA vendors on resolutions.
Requirements
Bachelor’s degree in electrical engineering, computer engineering, computer science, or a related technical field, or equivalent practical experience.
At least 10 years of hands-on experience in physical design and implementation, including synthesis, place and route, timing convergence, and physical verification.
Proficiency with EDA tools including Innovus, Tempus, and Quantus, with a deep understanding of physical design flows and methodologies.
Ability to work to tight schedules and implement low-power design techniques.
Experience with System-on-Chip design and implementation.
Expertise in sub-7nm process node technologies.
Strong TCL scripting skills for developing custom flows and methodologies on Cadence and Synopsys EDA tools.
Culture & Benefits
Medical, dental, and vision insurance.
401(k) plan with matching contributions.
Short-term and long-term disability insurance.
Health Savings Account and Health Reimbursement Account options.
Paid sick leave, holidays, and vacation, plus tuition reimbursement and growth opportunities.
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