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5 дней назад

Physical Design Engineer (ASIC)

112 200 - 165 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Physical Design Engineer (ASIC): Executing synthesis, place and route, static timing analysis, and signoff for ASIC partitions with an accent on sub-7nm SoC implementation, low-power design, and physical verification. Focus on closing EM/IR, driving LEC convergence, developing TCL-based EDA flows, and resolving implementation issues with design teams and EDA vendors.

Location: Complete on-site at San Jose, California; must be able to travel to an Arrow client office location as requested by client leadership.

Annual hiring range: $112,200–$165,000.

Company

eInfochips, an hirify.global company, provides product engineering and semiconductor design services, including ASIC and connected-product development across multiple industries.

What you will do

  • Execute synthesis, place and route, and static timing analysis for assigned ASIC chip partitions.
  • Collaborate with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues.
  • Close electromigration and IR issues and drive logical equivalence checking and physical verification signoff.
  • Identify physical design challenges and support efficient design iteration and convergence.
  • Refine synthesis, place-and-route, EM/IR, power delivery network, and logical equivalence checking methodologies.
  • Troubleshoot implementation flow issues and work with EDA vendors on resolutions.

Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, computer science, or a related technical field, or equivalent practical experience.
  • At least 10 years of hands-on experience in physical design and implementation, including synthesis, place and route, timing convergence, and physical verification.
  • Proficiency with EDA tools including Innovus, Tempus, and Quantus, with a deep understanding of physical design flows and methodologies.
  • Ability to work to tight schedules and implement low-power design techniques.
  • Experience with System-on-Chip design and implementation.
  • Expertise in sub-7nm process node technologies.
  • Strong TCL scripting skills for developing custom flows and methodologies on Cadence and Synopsys EDA tools.

Culture & Benefits

  • Medical, dental, and vision insurance.
  • 401(k) plan with matching contributions.
  • Short-term and long-term disability insurance.
  • Health Savings Account and Health Reimbursement Account options.
  • Paid sick leave, holidays, and vacation, plus tuition reimbursement and growth opportunities.

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