IC Layout Engineer (AI Hardware)

Location: Hillsboro, Oregon, United States; hybrid with 80% onsite work. US work authorization is required; visa sponsorship is not available.

Company

hirify.global is an independent research and analysis firm covering the semiconductor supply chain, AI hardware, software, and infrastructure through technical research, industry models, consulting, and due diligence.

What you will do

• Analyze the physical design and layout of GPUs, ASICs, CPUs, custom accelerators, high-speed I/O, memory subsystems, and advanced packaging.
• Interpret digital and analog floorplans, functional blocks, hierarchy, power and clock distribution, I/O placement, and standard-cell utilization from die-level imagery.
• Evaluate area, timing, power, placement density, process-node, and physical implementation trade-offs across competing hardware designs.
• Analyze analog and mixed-signal regions such as SerDes, PLLs, PHYs, and power-management circuits, including matching, isolation, shielding, and routing choices.
• Drive end-to-end teardowns and characterization, operate analytical toolchains, and plan specialized physical and electrical analysis.
• Co-author technical research and translate physical evidence into competitive, architectural, and roadmap insights.

Requirements

• US work authorization required; no visa sponsorship available.
• At least 2 years of industry experience in IC layout, physical design, place-and-route, custom or analog layout, or closely related work is preferred; exceptional candidates at other experience levels are considered.
• Strong knowledge of digital and/or analog physical design flows, including floorplanning, placement, CTS, routing, and signoff on advanced process nodes.
• Working knowledge of standard-cell architectures, utilization metrics, and area, power, and performance optimization.
• Knowledge of AI and datacenter hardware architecture, including GPUs, CPUs, and accelerators, plus physical or electrical failure analysis and root-cause investigation.
• Hands-on experience with or strong aptitude for semiconductor sample preparation and analytical tools such as precision polishing, FIB, SEM, electron-beam, X-ray, and compositional methods.

Nice to have

• Experience with Innovus, Fusion Compiler, Virtuoso, and GDS/OASIS-level layout detail.
• Analog/mixed-signal layout expertise, advanced packaging experience, and knowledge of 2.5D/3D integration, high-speed interconnects, or hybrid bonding.
• Experience interpreting micrographs and electrical measurements to infer cell libraries, track heights, fin or nanosheet configurations, and metal-stack usage.
• Python experience for image analysis, layout-metric extraction, automation, and engineering data analysis.
• Statistical and process-control literacy, a strong expert network, or experience developing physical and electrical failure-analysis toolchains.

Culture & Benefits

• Work independently while collaborating with a globally distributed analyst team.
• Contribute to research published for a large audience across the semiconductor and AI industries.
• Build expertise in next-generation AI hardware, chiplets, heterogeneous compute, advanced packaging, HBM, and optical interconnects.
• Develop cross-layer knowledge spanning device physics, manufacturing, layout, system architecture, and workload optimization.
• Participate in industry engagement, conferences, expert interactions, and thought leadership.