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10 дней назад

ASIC Implementation Specialist

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Netherlands
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
ASIC Implementation Specialist (ASIC/RTL-to-GDSII): Driving physical implementation and signoff for greenfield ASIC projects supporting high-performance trading systems with an accent on floorplanning, clock-tree synthesis, timing closure, and physical verification. Focus on optimizing advanced FinFET designs, improving implementation automation, and coordinating RTL, DFT, packaging, and foundry integration.

Location: Amsterdam, Netherlands

Company

Research-driven trading firm developing proprietary systems and algorithms using quantitative modeling, machine learning, and engineering for global markets.

What you will do

  • Own ASIC blocks across the RTL-to-GDSII back-end flow, including synthesis, floorplanning, clock-tree synthesis, timing optimization, and signoff.
  • Design floorplans and power grids, making decisions on macro and pin placement, area budgets, and clock-tree optimization.
  • Drive static timing analysis and timing closure for high-performance designs, including development and validation of SDC constraints.
  • Prepare designs for signoff through power integrity analysis, physical verification, logic equivalence checking, and engineering change orders.
  • Improve implementation flows by developing automation and scripts, and use implementation insights to influence RTL design.
  • Collaborate with RTL design, DFT, packaging, and foundry teams; contribute through design reviews and documentation.

Requirements

  • BS or MS in Electrical Engineering or Computer Engineering and 7+ years of ASIC implementation experience with multiple successful tapeouts.
  • Strong experience in physical implementation and signoff, including floorplanning, clock-tree synthesis, static timing analysis, timing closure, and physical verification.
  • Hands-on experience with Cadence and Siemens implementation and signoff tools.
  • Strong understanding of CMOS, RC-parasitic extraction, and physical design formats and constraints.
  • Experience with low-power design flows and awareness of design-for-test requirements.
  • Experience with advanced FinFET nodes, including 16, 12, 7, or 5 nm.

Nice to have

  • Experience with custom macro integration.
  • Knowledge of package/PCB co-design, chiplets, or 2.5D/3D integration.
  • Exposure to machine-learning-driven implementation flows.
  • RTL coding ability and functional verification experience.
  • Synthesis and DFT experience.

Culture & Benefits

  • Work on greenfield projects spanning cutting-edge research and production-scale implementations.
  • Contribute to ASIC technology supporting trading systems over the next decade.
  • Work in a research-driven environment combining quantitative modeling, machine learning, engineering, and real-time feedback.

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