data analysisatesemiconductorfailure analysisyield optimizationdesign for manufacturabilityanalog mixed signaldesign for testability
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
Пожаловаться
Зарплата и рынок
Мало
95к-122к CAD/год
95к CAD120к CADмедиана140к CAD
По похожим ролям (50) ~ 120к CAD/год
На СНГ рынке: $1.9к/мес ($1.8к - $3к)
64
Средняя вакансия
развернуть
Обязанности чётко описаны и дают серьёзную ответственность за передовые полупроводниковые продукты, но зарплата ниже ориентира для похожих senior-позиций, что снижает привлекательность предложения.
Кликните для подробной информации
Ниже рынкаСовременные технологииПонятные обязанностиПолный цикл продуктаИнфраструктура ИИ
Оценка от Hirify AI
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Подключить Plus
Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior NPI Product Engineer (Semiconductor): Leading new product introduction for high-performance analog and mixed-signal semiconductor ICs from concept through high-volume manufacturing and end-of-life with an accent on design for testability, characterization, ATE correlation, and yield optimization. Focus on analyzing process, voltage, and temperature data, resolving yield limiters and manufacturing failures, and transferring products into production.
Location: GBR - Stansted, United Kingdom; hybrid model with 4 days in the office from Monday to Thursday
Salary: CAD 95,000–122,000 per year
Company
hirify.global develops high-performance optical and analog/mixed-signal semiconductor IC solutions for AI data centers, PON, and 5G wireless networks.
What you will do
Lead NPI activities from product concept through final release, high-volume manufacturing transfer, and product lifecycle maintenance.
Coordinate with Design, Test, Validation, Quality, Reliability, Applications, Operations, and other cross-functional teams.
Define Design for Manufacturability and Design for Testability requirements and support ATE test program development, verification, and optimization.
Plan and execute wafer-level and bench characterization, PVT analysis, ATE-to-bench correlation, and datasheet validation.
Run design of experiments, yield analysis, process capability studies, test-time reduction, and yield-limiter investigations.
Resolve manufacturing and field-return issues through failure analysis, root-cause investigation, corrective actions, and continuous improvement.
Requirements
BSc in Electrical Engineering or a related field and at least 8 years of relevant experience.
Experience in semiconductor technology, product engineering, test engineering, or design engineering.
Experience with corrective actions, 8D reports, non-conformance reports, and failure analysis reports.
Knowledge of statistical theory and data analysis tools such as Excel, JMP, Galaxy, or dataConductor.
Strong knowledge of high-speed serial digital interconnect components and test methodologies.
Experience with JEDEC and/or MIL quality requirements.
Nice to have
Experience with high-speed digital ATE platforms such as Advantest or Teradyne, or equivalent rack solutions.
Culture & Benefits
Work within a cross-functional NPI engineering team responsible for the full product lifecycle.
Opportunity to contribute to advanced CMOS and BiCMOS products operating at data rates of 25–400 Gbps and beyond.
Provide technical guidance and mentorship to junior product engineers.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →