Functional Safety & RAS Lead (RISC-V)

Location: Santa Clara, California, United States

Base pay range: $279,504.00–$341,616.00 per year, plus potential variable or incentive compensation and equity.

Company

hirify.global develops RISC-V compute platforms for high-performance and data-intensive applications across automotive, artificial intelligence, machine learning, robotics, data center, mobile, and consumer markets.

What you will do

• Work with customers, technical architects, and engineering teams to define functional safety and RAS requirements from safety goals through development, assessment, release, and customer support.
• Apply functional safety expertise, particularly ISO 26262, to processor and SoC products.
• Define program scope, milestones, dependencies, risks, and engineering resource needs.
• Coordinate architecture, design, verification, software, quality, program management, product, sales, applications, and customer-facing teams.
• Maintain traceability of safety requirements and decisions through implementation, verification, documentation, product changes, and releases.
• Identify technical risks, including dependent failures and common-cause concerns, and support customer assessments, audits, reviews, and certification activities.

Requirements

• 10+ years of experience in functional safety, RAS, hardware reliability, or related work in semiconductor, processor, SoC, or complex hardware development.
• 5+ years of semiconductor, SoC, processor-IP, or complex hardware development experience, including significant architecture or technical-leadership responsibility.
• Bachelor’s or Master’s degree in electrical engineering, computer engineering, computer science, or a related technical discipline, or equivalent experience.
• Deep experience with ISO 26262 and methods including FMEDA, FMEA, fault-tree analysis, diagnostic coverage, safety cases, and fault injection.
• Strong understanding of SoC and IP development, RAS mechanisms, hardware random-failure detection, containment, redundancy, lockstep, ECC/parity, memory protection, and recovery.
• Successful background and reference checks, proof of the right to work in the United States, and authorization to access export-controlled technology or obtain the required export approvals.

Nice to have

• Experience with RISC-V processor or SoC architecture and automotive semiconductor IP developed to ASIL-B or ASIL-D objectives.
• RAS experience in data center, AI, robotics, or other high-availability compute products.
• Reliability analysis or testing experience, including soft-error-rate modeling or radiation testing.
• Experience with certification bodies or external assessors and active participation in standards communities.
• Familiarity with ISO/SAE 21434 or cybersecurity engineering.

Culture & Benefits

• Collaborative work across architecture, engineering, product, customer, and standards communities.
• Healthcare and retirement plans, paid time off, and other comprehensive benefits.
• Potential variable or incentive compensation and equity in addition to base pay.
• Inclusive equal-opportunity workplace committed to diversity.