Microarchitecture and Design Engineer (AI SoC)

Location: Hybrid role based at an hirify.global site in Santa Clara or Folsom, California, United States

Annual salary: $105,650–$172,860 USD

Company

hirify.global designs and manufactures silicon products, including AI hardware for edge devices and data center accelerators.

What you will do

• Develop logic design, RTL coding, and simulation for SoC designs.
• Define and implement architecture and microarchitecture features for logic blocks.
• Optimize RTL against power, performance, area, and timing targets.
• Perform RTL, timing, power, and design-integrity quality checks.
• Collaborate with IP providers to integrate and validate IPs at the SoC level.
• Support verification planning, resolve RTL test failures, and apply secure development and quality-assurance practices through IP and SoC handoff.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field plus 1+ year of hands-on experience in logic design, RTL coding, and simulation through internships, academic projects, coursework, training, or professional work, or a master’s degree in a related field with no prior professional experience.
• Proficiency in RTL coding languages such as Verilog or VHDL.
• Familiarity with logic design tools and methodologies for synthesis, timing analysis, and power optimization.
• Knowledge of SoC design principles and IP integration.

Nice to have

• Strong analytical and problem-solving skills with attention to detail.
• Effective communication and collaboration skills for cross-functional teamwork.
• Interest in secure design practices and quality-assurance processes.

Culture & Benefits

• Hybrid work model combining on-site work at the assigned hirify.global site with off-site work.
• Competitive compensation package with stock bonuses.
• Health, retirement, and vacation benefits.
• Shift 1 schedule in the United States.
• Employment opportunity at a company focused on AI hardware and advanced silicon products.