AI Silicon Performance Modeling and Analysis Engineer

Location: Santa Clara, California, United States; hybrid work model with time split between the assigned Intel site and off-site work

Annual salary: $141,910–$232,190 USD

Company

hirify.global develops technology products and platforms; this role supports next-generation AI silicon performance engineering.

What you will do

• Develop, maintain, and improve SystemC/TLM-based performance models for AI SoC fabrics, memory subsystems, scale-up and scale-out interconnects, host-device memory paths, and end-to-end data movement.
• Define validation strategies, regression suites, coverage methods, and quality metrics; correlate models with architectural expectations, reference simulations, projections, and hardware measurements.
• Conduct performance studies across workloads, traffic patterns, and system configurations, analyzing bandwidth, latency, congestion, buffering, resource utilization, and scalability.
• Build automated workflows, analytics frameworks, dashboards, and visualization tools for large-scale performance data using Python.
• Identify bottlenecks, evaluate architectural tradeoffs, and present data-backed recommendations to architects, designers, product stakeholders, and engineering leadership.
• Improve modeling and analysis methodologies, mentor junior engineers, and contribute to technical leadership and knowledge sharing.

Requirements

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or Electronics Engineering.
• 6+ years of industry experience in performance modeling, AI silicon architecture, SoC architecture, computer architecture, performance engineering, or related domains.
• Experience with SoC architecture, on-chip communication fabrics, NoC concepts, high-speed interconnects, and scale-up/scale-out communication architectures.
• Experience with memory subsystem architecture, including memory controllers, cache hierarchies, data movement, latency and bandwidth characterization, and performance bottleneck analysis.
• Software development experience in C++ and working proficiency in Python for automation, performance analysis, data processing, and visualization.
• Hands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.
• Experience developing or validating performance models for AI accelerators, SoCs, CPUs, GPUs, networking products, or complex hardware systems.
• Experience performing architectural tradeoff analysis, performance debugging, and characterization studies.
• Strong quantitative reasoning, analytical problem-solving, communication, collaboration, technical presentation, stakeholder management, independent execution, and decision-influence skills.
• This position is not eligible for Intel immigration sponsorship.

Nice to have

• Deep understanding of AI accelerator architectures and modern AI infrastructure.
• Experience modeling memory, communication, interconnect, or scalability-related subsystems and analyzing NoC performance.
• Understanding of scale-up and scale-out architectures used in modern AI computing platforms.
• Familiarity with AI/ML workloads, large language models, distributed training, and inference environments.
• Experience with performance stimulus generation, workload characterization, large-scale distributed AI systems, and accelerator clusters.
• Experience building automated dashboards and reporting solutions with Power BI, Tableau, Grafana, Plotly, or similar tools.
• Experience mentoring engineers and providing technical leadership in cross-functional environments.

Culture & Benefits

• Full-time hybrid work model combining on-site work at the assigned site with off-site work.
• Competitive annual compensation, stock bonuses, health benefits, retirement benefits, and vacation.
• Cross-functional collaboration with architecture, performance stimulus, silicon design, and product teams.
• Technical environment focused on rigorous analysis, continuous improvement, and technical excellence.
• Employment practices provide equal consideration without regard to protected characteristics.