В OpenAI это четко очерченная ведущая роль в разработке передового AI-железа с ответственностью за весь цикл и задачами по защите кремния; главное ограничение - работа в США и возможные требования экспортного контроля.
Ограничения по статусу
Передовой AI-домен
Ответственность за весь цикл
Актуальные технологии
Выше рыночного уровня
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Silicon Design Lead (AI hardware/security): Driving architecture, microarchitecture, and implementation of silicon IP and subsystems for AI-native hardware platforms with an accent on hardware security, performance, power, area, and design complexity. Focus on translating security requirements and threat models into silicon capabilities, integrating encryption and access controls, and coordinating RTL, verification, firmware, and software execution.
Location: San Francisco, United States; hybrid
Salary: $287K–$485K annually plus equity
Company
OpenAI is an AI research and deployment company developing products and systems intended to ensure that general-purpose artificial intelligence benefits humanity.
What you will do
Own architecture, microarchitecture, implementation, integration, and validation of silicon IP and subsystems for AI hardware platforms.
Define hardware interfaces, data flows, and microarchitectural tradeoffs against functional, performance, power, and area requirements.
Translate security architecture, requirements, and threat models into implementable hardware capabilities in partnership with the Security team.
Design and integrate encryption, key management, access controls, isolation, and data protection across silicon subsystems.
Review RTL implementations and collaborate with silicon architecture, verification, firmware, and software teams on subsystem execution.
Evaluate existing and third-party IP, identify gaps, and drive solutions across subsystem boundaries.
Requirements
Strong experience in silicon IP or subsystem-level architecture, microarchitecture, and implementation.
Experience owning hardware IP or subsystem designs from architectural definition through implementation and integration.
Experience implementing hardware security features such as memory encryption, key management, access controls, isolation, or secure boot.
Ability to translate functional and security requirements into hardware architectures, interfaces, and microarchitectural specifications.
Working knowledge of RTL design and coding proficiency in Verilog or SystemVerilog, including the ability to read, review, and contribute to RTL.
Ability to evaluate performance, power, area, and complexity tradeoffs across silicon designs.
Ability to work across security, silicon architecture, RTL, verification, firmware, and software teams from concept through execution.
Candidates may need to meet certain legal status requirements under U.S. export control laws and regulations.
Nice to have
Broader SoC-level architecture or integration experience; deep IP or subsystem-level expertise is sufficient.
Culture & Benefits
Hybrid work arrangement in San Francisco.
Full-time employment with equity included in the compensation package.
Commitment to safety, inclusion, equal opportunity, reasonable accommodations, and compliance with applicable employment laws.
Background checks are administered in accordance with applicable law.
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