Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Роль дает редкий доступ к передовым AI-чипам и понятный путь к экспертному росту, но зарплата не раскрыта, а работа в офисе 80% времени ограничивает гибкость.
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Зарплата не указанаПочти всегда в офисеПередовой AI-секторПонятная рольРост до эксперта
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Hardware Engineer, Design Expert, or Architect (AI Hardware): Analyzing the architecture, design, manufacturing, and packaging of AI and datacenter hardware with an accent on teardown, characterization, failure analysis, and DTCO/STCO trade-offs. Focus on interpreting physical evidence and electrical measurements, developing analytical toolchains, and translating hardware findings into technical research.
Location: 80% onsite in Hillsboro, Oregon, United States; office hours
Company
hirify.global is an independent research and analysis firm specializing in the semiconductor and AI industries, covering the supply chain from fabrication and hardware to AI models, software, and infrastructure.
What you will do
Analyze the architecture of AI and datacenter hardware, including GPUs, ASICs, CPUs, custom accelerators, high-speed I/O, memory subsystems, and packaging.
Lead end-to-end hardware teardowns and characterization using analytical tools and specialized expertise.
Identify competitive advantages, design trade-offs, generational changes, and process-design interactions.
Apply DTCO and STCO reasoning to interpret architecture, manufacturing, and system-level decisions.
Co-author technical research based on physical observations, cross-industry context, and engineering analysis.
Help expand the laboratory’s capabilities, toolchains, and research output.
Requirements
At least 2 years of experience in hardware architecture, product design, silicon engineering, post-silicon debug, or an equivalent field, with exposure to leading-edge components.
Strong knowledge of AI and datacenter hardware architecture, including GPUs, CPUs, and accelerators on advanced process nodes.
Experience with physical or electrical failure analysis, fault isolation, device debugging, or related root-cause investigation.
Understanding of Design Technology Co-Optimization principles.
Experience with, or strong aptitude for working with, semiconductor sample preparation and analytical tools such as FIB, SEM, TEM, X-ray, and compositional analysis.
US work authorization is required; visa sponsorship is not available.
Nice to have
Experience in advanced packaging, including 2.5D/3D integration, high-speed interconnects, or hybrid bonding.
Knowledge of advanced manufacturing across CMOS logic, memory, and emerging technologies.
Ability to interpret micrographs and electrical measurements and develop physical and electrical failure-analysis toolchains.
Python experience for data analysis and engineering tasks.
Statistical and process-control literacy or a strong professional network of industry experts.
Culture & Benefits
Work with a globally distributed team of more than 50 analysts and experts across the semiconductor supply chain and AI ecosystem.
Contribute to industry research, models, consulting, technical due diligence, and public equity markets analysis.
Build expertise in next-generation AI architectures, chiplets, heterogeneous computing, advanced packaging, HBM, and optical interconnects.
Develop cross-layer knowledge spanning device physics, manufacturing, system architecture, workload optimization, and data-driven analysis.
Progress toward a senior architect or subject matter expert role with influence over research direction and technical coverage.
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