CPU Physical Design Engineer

Location: On-site in Austin, Texas, United States

Annual salary: $105,650–$200,340 USD

Company

hirify.global develops advanced processor technologies and semiconductor products for client, data center, and AI computing.

What you will do

• Implement CPU physical designs from RTL through manufacturing-ready design databases.
• Execute physical design flows including floorplanning, synthesis, place and route, clock tree synthesis, static timing analysis, power distribution, and optimization.
• Perform formal equivalence, reliability, layout, and structural design verification and signoff.
• Analyze power, performance, area, timing, and overall design quality to identify improvements.
• Collaborate with architecture, logic, circuit, validation, design automation, and EDA engineering teams.
• Develop physical design methodologies, automation, and improved tool capabilities.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience, or a master's degree with 1+ years of educational or work experience.
• Experience implementing physical designs with industry-standard EDA tools such as Synopsys Fusion Compiler, Cadence Genus/Innovus, or equivalent.
• Experience with backend physical design workflows, including floorplanning, place and route, clock tree synthesis, static timing analysis, and layout verification.
• Scripting experience with TCL, Perl, Python, or similar languages for design automation and analysis.
• Experience with RTL-to-GDS physical design flows.
• Ability to work on-site in Austin, Texas, United States.

Nice to have

• CPU, SoC, or other complex high-performance physical design experience.
• Tape-out experience with advanced semiconductor process technologies.
• Experience with low-power design, multiple power domains, UPF, power analysis, or PPA and timing optimization.
• RTL-to-GDS automation, multiple EDA platforms, or collaboration with EDA vendors.
• AI/ML-based approaches to place-and-route or physical design optimization.
• PhD in a relevant field with 6+ months of educational or work experience.

Culture & Benefits

• Collaboration across global, multidisciplinary engineering teams.
• Opportunities to work with advanced semiconductor technologies and next-generation CPU products.
• Health, retirement, vacation, stock bonuses, and other employee benefits.
• Focus on technical curiosity, continuous learning, ownership, and solving complex engineering problems.