AI Hardware Analyst

Location: United States, New York, Mexico, San Francisco, or Canada; in-office or remote. Work hours: office hours.

Company

hirify.global is an independent research and analysis firm focused on the semiconductor and AI industries, covering chips, software, infrastructure, supply chains, industry models, research, consulting, and technical due diligence.

What you will do

• Build first-principles performance models for LLM inference and training.
• Analyze arithmetic intensity, roofline performance, prefill and decode behavior, KV cache capacity, memory bandwidth, batching, parallelism, and latency-throughput trade-offs.
• Evaluate GPUs, TPUs, custom ASICs, emerging accelerators, HBM, memory systems, interconnects, racks, pods, and datacenters.
• Assess semiconductor manufacturing, packaging, yield, die cost, power, cooling, and system design trade-offs.
• Validate models against benchmarks and independent performance data, comparing theoretical and delivered application performance.
• Publish technical research, contribute to TCO and tokenomics models, and present findings to engineering, investment, and client audiences.

Requirements

• Deep technical understanding of compute hardware across silicon, systems, networking, clusters, or datacenters.
• Strong quantitative reasoning and ability to work with FLOPs, bytes, bandwidth, latency, joules, watts, and dollars.
• Knowledge of AI workload behavior, memory systems, interconnect communication, collective operations, and compute utilization.
• Working understanding of semiconductor manufacturing and economics, including process nodes, die size, yield, packaging, and HBM integration.
• Ability to develop structured models, validate assumptions, explain complex findings clearly, and take ambiguous questions through analysis and publication.
• Ability to work in the United States, New York, Mexico, San Francisco, or Canada, with availability during office hours.

Nice to have

• Experience with vLLM, SGLang, TensorRT-LLM, PyTorch, JAX, CUDA, Triton, or HIP.
• Experience with GPU or accelerator clusters, datacenter networking, rack-scale architecture, power, cooling, or large AI infrastructure.
• Semiconductor process, foundry, product engineering, yield, packaging, test, die cost modeling, teardown, or benchmarking experience.
• Technical publications, research papers, open-source contributions, benchmarks, hardware teardowns, or industry analysis.

Culture & Benefits

• Opportunity to expand from an existing specialization into the complete AI hardware stack.
• Ability to develop expertise in accelerator, HBM, networking, power, cooling, TCO, and infrastructure analysis.
• Strong performers can define and own a research coverage area based on their technical strengths.
• Opportunity to become a technical authority through research, publications, client briefings, and industry collaboration.