Full Chip Timing Modeling and Integration Engineer (FPGA)

Location: San Jose, California, United States

Salary: $133,200–$192,825 USD annually for the Bay Area, California.

Company

hirify.global develops Field-Programmable Gate Array (FPGA) solutions and next-generation FPGA products using advanced semiconductor process technologies.

What you will do

• Develop timing methodologies and execute full-chip timing for next-generation FPGA products.
• Define timing modeling strategies with cross-functional design teams.
• Generate, integrate, and validate high-level timing models.
• Perform full-chip timing analysis, including clocking and timing constraint development.
• Analyze extraction issues, design margins, timing signoff requirements, and timing quality checks.
• Debug critical design issues, improve timing workflows, and communicate technical trade-offs across multi-site teams.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus 5+ years of industry experience in SoC development.
• 5+ years of experience with advanced semiconductor process nodes, timing formats, and design constraints including Liberty, Verilog, and Synopsys Design Constraints (SDC).
• 5+ years of experience with Static Timing Analysis (STA), including correlation of STA results with SPICE.
• 5+ years of experience in timing modeling, library quality assurance, and silicon modeling concepts such as LVF and POCV.
• 5+ years of experience writing Python and Tcl scripts for design automation.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• 7+ years of relevant industry experience.
• Experience with complex designs involving multiple voltage domains and functional or Design-for-Test (DFT) operating modes.
• Experience with FPGA, DDR, PCIe, or related technologies.
• Experience applying AI/ML techniques to improve and optimize execution.

Culture & Benefits

• Regular full-time employment in a fast-paced, high-performance design environment.
• Collaboration with cross-functional and multi-site teams.
• Incentive opportunities based on individual and company performance.
• Work across advanced semiconductor technologies and next-generation FPGA products.