Teach Lead Physical Design Engineer (Semiconductor)

Location: Singapore, Singapore

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions based on CXL, Ethernet, NVLink, PCIe, and UALink technologies, supported by its COSMOS software suite.

What you will do

• Perform block-level and top-level physical implementation for high-speed transceiver designs at TSMC 3nm and advanced technology nodes.
• Handle floorplanning, placement, clock tree synthesis, routing, physical verification, ECO implementation, and tapeout signoff support.
• Collaborate with RTL and STA teams on timing, area, and power convergence.
• Optimize EM/IR performance, power grids, congestion, clock skew, clock quality, and RC-aware placement and routing.
• Integrate high-speed IPs and top-level blocks with aligned physical interfaces, constraints, and timing.
• Develop Tcl, Python, or Perl automation scripts to improve physical design flows and productivity.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 5+ years of physical design experience, preferably with advanced technology nodes.
• Strong experience with floorplanning, placement, CTS, routing, IR drop mitigation, timing closure, and physical verification.
• Hands-on experience with ICC2, Innovus, Calibre, Voltus, RedHawk, and related industry-standard tools.
• Experience integrating SerDes or PHY IPs into SoC or chiplet-based environments and working with high-frequency datapath and DSP-related designs.
• Solid scripting, problem-solving, and cross-functional collaboration skills.

Culture & Benefits

• Work with a high-performance design team developing next-generation semiconductor connectivity solutions.
• Inclusive environment that encourages applications from people with diverse backgrounds and experiences.