Senior DFT Engineer (ASIC)

Location: Singapore-Yishun; onsite role

Company

hirify.global develops semiconductor solutions involving complex SoC and ASIC designs.

What you will do

• Develop and implement block-level and top-level DFT architectures for hierarchical SoC and ASIC designs.
• Perform scan insertion, test point insertion, and test compression using SSN or equivalent architectures.
• Validate SSN topology, balance scan chains, manage clock-domain crossings, and integrate IEEE 1149.x boundary scan.
• Generate and analyze ATPG patterns for stuck-at, transition, and path-delay faults.
• Perform DFT verification through Verilog and gate-level simulation.
• Collaborate with physical design and ATE teams on timing, STIL/WGL pattern validation, silicon bring-up, and production test debugging.

Requirements

• Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
• At least 3 years of experience in DFT design and verification; 5+ years is preferred for senior roles.
• Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Hands-on experience with DFT tools such as Siemens Tessent and with ATPG generation, fault-coverage analysis, and gate-level verification.
• Familiarity with ATE test flows and platforms such as Advantest or Teradyne.
• Strong scripting skills in TCL, Perl, or Python.

Culture & Benefits

• Full-time employment.
• Cross-functional collaboration with physical design, ATE, and testing teams.
• Equal opportunity employment in accordance with applicable law.