Physical Design Intern (ASIC/AI)

Location: Singapore

Company

hirify.global develops semiconductor solutions and ASIC technologies for enterprise, cloud, AI, and carrier infrastructure.

What you will do

• Implement block-level layouts and perform timing closure for complex SoC designs.
• Support static timing and crosstalk analysis, synthesis, and physical synthesis.
• Perform power, IR drop, and electromigration analysis.
• Execute physical verification, including LVS, DRC, ERC, and antenna checks.
• Implement engineering change orders and contribute to RTL-to-GDS design flows.

Requirements

• Currently pursuing a Master's degree in electronic engineering, microelectronics, or a related discipline.
• Basic understanding of semiconductor devices and electronic circuits.
• Experience with scripting or programming using Tcl/Tk, Perl, or Python.
• Detail-oriented, self-motivated, collaborative, and able to communicate effectively in writing and verbally.
• Eligible to access export-controlled information under applicable U.S. regulations; an export license review may be required before employment.

Nice to have

• Experience with physical design and automatic place-and-route tools, including Synopsys or Cadence tools.
• Experience with synthesis or static timing analysis.

Culture & Benefits

• Competitive compensation and benefits.
• Collaborative, transparent, and inclusive work environment.
• Resources and support for professional growth and development.
• Interviews are designed to assess individual experience, reasoning, and communication without unauthorized AI assistance.