Staff Layout Engineer (IC Layout)

Location: Singapore-Yishun; must be available to relocate to Singapore immediately

Company

hirify.global develops semiconductor technologies, with this role supporting the Library Group within the Central Engineering Group.

What you will do

• Design and develop layouts for memory, I/O, and standard-cell libraries.
• Apply layout guidelines, new process rules, and technical requirements to deliver high-quality layouts.
• Plan layout floor-planning and project schedules.
• Complete layout and physical verification within the planned schedule.
• Review new technologies and document layout methodologies, flows, and guidelines.
• Lead or train junior layout engineers and collaborate across the library team.

Requirements

• Minimum 8 years of IC layout experience.
• Strong experience with submicron processes, including 16nm, 7nm, 5nm, 2nm, A14, and below.
• Experience in digital layout for standard cells, memory, and I/O; memory layout topology knowledge is required.
• Experience with Cadence Layout and schematic capture, Virtuoso XL/VXL/EXL, and Calibre verification tools.
• Experience with LVS, DRC, ERC, antenna, and electromigration verification in CMOS processes.
• Must be available to relocate to Singapore immediately.

Nice to have

• Analog layout experience.
• Memory compiler experience.
• Script programming and SKILL programming knowledge.

Culture & Benefits

• Work independently and collaboratively within the library team.
• Opportunity to contribute to new technology reviews and layout methodology development.
• Equal opportunity employment.