Principal Physical Design Engineer

Location: Singapore, Singapore

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

• Perform block-level and top-level physical implementation, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Collaborate with RTL and STA teams on timing, area, and power convergence.
• Optimize EM/IR performance, power grids, congestion, clock skew, clock quality, and RC extraction-aware placement and routing.
• Integrate high-speed IPs and top-level blocks with aligned physical interfaces, constraints, and timing.
• Implement ECOs and support tapeout signoff while maintaining DRC, LVS, ANT, CELL, and ERC-clean databases.
• Develop automation scripts in Tcl, Python, or Perl to improve physical design flows and productivity.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 5–10 years of physical design experience, preferably with advanced technology nodes.
• Strong experience with floorplanning, placement, CTS, routing, IR drop mitigation, signoff debugging, and timing closure.
• Hands-on experience with Synopsys ICC2, Cadence Innovus, Calibre, and Voltus.
• Experience integrating SerDes or PHY IPs into SoC or chiplet-based environments.
• Experience with high-frequency datapath and DSP-related designs, scripting, problem-solving, and cross-functional collaboration.

Culture & Benefits

• Work with diverse teams and perspectives across next-generation AI infrastructure projects.
• Inclusive environment encouraging applications from people with varied backgrounds and experiences.