Senior Analog Mixed-Signal IC Layout Engineer

Location: Singapore, Singapore

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, including CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Design and verify ASIC blocks using leading-edge methodologies and tools.
• Work on high-performance compute and networking standards in advanced CMOS process nodes.
• Apply analog, mixed-signal, VLSI, and hardware engineering expertise to real-world systems.
• Contribute to designs involving high-speed interfaces such as PCIe, DDR, HBM, and SerDes.
• Support design verification and validation using RTL languages, UVM, functional coverage, and assertions.

Requirements

• Pursuing a BS or MS in electrical engineering, computer science, or a related field.
• Hardware engineering background with an emphasis on VLSI or computer architecture.
• Exposure to digital design or verification, VLSI design and circuits, and computer architecture.
• Hands-on knowledge of Verilog and SystemVerilog RTL design languages and tools.
• Familiarity with verification methodologies including UVM, functional coverage, and assertions.
• Hands-on experience with C/C++ and familiarity with scripting languages such as Python or Perl.

Nice to have

• Real-world design or verification experience in Verilog or SystemVerilog.
• Knowledge of PCIe, DDR, HBM, or SerDes high-speed interfaces.
• Familiarity with Synopsys EDA tools.

Culture & Benefits

• Work in a diverse environment that encourages creativity, innovation, and varied backgrounds and experiences.
• Applications are encouraged from people with relevant experience across diverse communities, including veterans, parents, people with disabilities, LGBTQ+ and non-binary people, and people of color.