Product Failure Analysis Engineer (SCAN Design for Test)

Location: Hillsboro, Oregon, United States; hybrid work model with time split between the hirify.global site and off-site work

Annual salary: $141,910–$269,100 USD

Company

hirify.global designs and manufactures advanced semiconductor technologies, including products for personal computing, data centers, AI systems, and autonomous vehicles.

What you will do

• Lead failure analysis investigations using FIB tools, probe tools, automated systems, and other laboratory equipment.
• Apply logical diagnosis and physical failure analysis to isolate silicon defects and identify root causes.
• Collaborate with DFT, design, test, validation, process integration, yield engineering, and high-volume manufacturing teams.
• Develop debug tools, automation frameworks, methodologies, and diagnostic capabilities for advanced technology products.
• Evaluate design-for-debug and physical design issues, implement mitigations, and drive permanent corrective actions.
• Support product quality, yield, reliability, production qualification, and time-to-market for hirify.global Foundry 18A products.

Requirements

• 6+ years of hands-on semiconductor, product engineering, failure analysis, silicon debug, DFT, yield engineering, or post-silicon validation experience, or an equivalent combination of advanced education and experience.
• Bachelor’s degree in electrical engineering, computer engineering, or a related STEM discipline; master’s or PhD pathways are also accepted with less experience.
• Expertise in DFT tools and techniques, SCAN ATPG methodology, scan chain diagnosis, fault modeling, and scan architecture.
• Experience with ATPG pattern generation, stuck-at, transition, path-delay and bridging faults, and fault-isolation techniques.
• Experience with Siemens Tessent, Synopsys TestMAX/TetraMAX, Verdi, DVE, simulation, and diagnosis tools.
• Experience developing debug automation and analysis tools using Python, Perl, or TCL.

Nice to have

• Experience with JTAG and validation or debug research methodologies.
• Experience developing innovative debug tools in a research-driven environment.
• Experience in foundry, fabless semiconductor, or high-volume manufacturing environments.

Culture & Benefits

• Hybrid work model combining on-site work at the assigned hirify.global site with off-site work.
• Competitive compensation with stock bonuses.
• Health, retirement, and vacation benefits.
• Cross-functional work focused on advanced semiconductor technology and continuous improvement.