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Зарплата не указанаРазный фокус ролиАктуальные технологииИнфраструктура для ИИНовый R&D-центр
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Текст:
Hirify AI/Оригинал
TL;DR
Principal Physical Design CAD Engineer (GenAI): Developing and improving CAD flows and automation infrastructure for advanced semiconductor implementation, from synthesis through place and route, timing closure, power optimization, and signoff readiness, with an accent on Synopsys Fusion Compiler, parasitic extraction, and GenAI-based engineering methods. Focus on building robust EDA automation, analyzing QoR, timing, congestion, power, and design-rule results, and solving complex physical design and debug challenges for high-speed AI infrastructure chips.
Location: Haifa District, Israel
Company
hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.
What you will do
Develop, maintain, and improve physical design CAD flows and methodologies using industry-standard EDA tools.
Build automation infrastructure for implementation, analysis, reporting, and debugging across large-scale design flows.
Support synthesis, floorplanning, placement, clock-tree synthesis, routing, timing closure, power optimization, physical verification, and signoff readiness.
Develop scripts and utilities to improve productivity, result quality, and flow robustness.
Support and enhance flows based on Synopsys Fusion Compiler and analyze timing, power, congestion, utilization, QoR, and design-rule results.
Explore and integrate GenAI solutions for debugging, repetitive-task automation, reporting, and engineering productivity.
Requirements
At least 3 years of experience in physical design, CAD, or implementation methodology.
Strong understanding of synthesis, placement, CTS, routing, timing closure, physical verification, timing, power, congestion, floorplanning, and QoR analysis.
Hands-on experience with Synopsys Fusion Compiler.
Experience with Tcl and Python scripting and automation around EDA tools and large-scale design flows.
Strong debugging and problem-solving skills, with the ability to work closely with multiple engineering teams.
Motivation to learn and apply GenAI technologies in semiconductor design flows.
Nice to have
Experience with PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar tools.
Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows.
Experience building dashboards, regression systems, flow checkers, or automated report analyzers.
Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding and debugging tools.
Experience with Git, CI/CD, databases, or cloud-based compute environments.
Culture & Benefits
Opportunity to join a strategic R&D center being established in Israel.
Work on semiconductor chips addressing data bottlenecks in large-scale AI infrastructure.
Inclusive environment that encourages applications from people with diverse backgrounds and experiences.
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