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1 час назад

Pre-Silicon Verification Engineer (SystemVerilog/UVM)

122 440 - 172 860$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Pre-Silicon Verification Engineer (SystemVerilog/UVM): Developing verification environments and tests for PLL and FLL clock-generator IPs with an accent on functional validation, pre-silicon debugging, and mixed-signal verification. Focus on building UVM testbenches, root-causing complex issues, validating AMS behavior, and collaborating with RTL, analog, and architecture teams.

Location: Hybrid role based at an hirify.global site in the United States, with primary location in Hillsboro, Oregon, and additional locations in Phoenix, Arizona; Folsom and Santa Clara, California; Beaver Brook, Massachusetts; and Austin, Texas.

Annual salary: $122,440–$172,860 USD

Company

hirify.global's Central Engineering Group develops internal products and external ASIC design services while improving engineering execution and supporting scalable product development.

What you will do

  • Develop SystemVerilog and UVM testbenches, verification environments, and tests for clock-generator IPs such as PLL and FLL.
  • Perform functional verification against microarchitecture specifications and maintain verification infrastructure across multiple IP generations.
  • Debug and root-cause pre-silicon issues within verification environments.
  • Lead mixed-signal validation activities, including AMS simulations, schematic debugging, and cross-functional issue resolution.
  • Document test plans and participate in technical reviews with architects, RTL developers, and analog design teams.
  • Contribute to architectural and microarchitectural feature definition and refinement.

Requirements

  • Bachelor's degree in Electrical or Computer Engineering or a related field with 4+ years of relevant experience; or a master's degree with 3+ years; or a PhD with 1+ years.
  • At least 2 years of experience with design verification and validation methodologies, UVM, SystemVerilog, and industry-standard EDA tools.
  • At least 2 years of experience with scripting languages such as Python and Perl.
  • Strong problem-solving, debugging, documentation, and cross-functional collaboration skills.
  • Ability to work in the hybrid US-based model at an assigned hirify.global site.

Nice to have

  • Expertise in SystemVerilog UVM coding and debugging.
  • Familiarity with PLL/FLL, SoC clocking, and related RTL development.

Culture & Benefits

  • Collaborative work with architecture, RTL, analog design, and other engineering teams.
  • Health, retirement, and vacation benefits.
  • Competitive pay and stock bonuses.
  • Hybrid work model combining on-site and off-site work.

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