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1 день назад

Principal ASIC Verification Engineer (Quantum Computing)

180 000 - 220 000$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal ASIC Verification Engineer (Quantum Computing): Leading functional verification of ASICs used in quantum computers based on optically trapped neutral atoms with an accent on block-to-chip verification, reusable Python testbenches, and post-layout gate-level simulation. Focus on closing coverage, debugging timing and DFT issues, coordinating verification work through tapeout, and supporting silicon bring-up and validation.

Location: Austin, TX; hybrid workplace

Base salary: $180,000–$220,000 per year, plus annual bonus and equity.

Company

hirify.global develops quantum computers using arrays of optically trapped neutral atoms.

What you will do

  • Own block-to-chip verification plans, schedules, signoff criteria, test development, and execution.
  • Develop Python testbenches, reusable drivers, monitors, reference models, scoreboards, and regression automation integrated with RTL simulators.
  • Lead post-layout gate-level verification, including netlist preparation, SDF annotation, and timing-accurate simulation.
  • Verify DFT test modes and patterns, debug resets, clock domains, X propagation, timing checks, and unresolved failures.
  • Provide technical direction, mentor engineers, coordinate contractors, review deliverables, and communicate verification risks.
  • Collaborate with architecture, RTL, firmware, hardware, DFT, and physical design teams through tapeout, silicon bring-up, and validation.

Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent experience.
  • 10+ years of ASIC/SoC verification experience; 15+ years preferred.
  • Experience verifying multiple ASICs through tapeout and subsequent silicon evaluation.
  • Strong Python, SystemVerilog, UVM, RTL debugging, HDL debug tools, Linux, and version control skills.
  • Experience with verification planning, SystemVerilog assertions, constrained-random testing, behavioral mixed-signal models, and functional and code coverage closure.
  • Hands-on experience with post-P&R netlists, SDF annotation, timing simulation, DFT flows, ATPG, MBIST, or JTAG.

Nice to have

  • Technical leadership through ASIC tapeout and experience directing verification contractors.
  • Silicon bring-up, lab debugging, and correlating hardware failures with simulation.
  • Experience with formal verification, equivalence checking, CDC/RDC, lint, emulation, or FPGA prototyping.
  • Familiarity with real-time control, signal processing, or quantum hardware.

Culture & Benefits

  • Fully paid medical, dental, and vision insurance for employees and dependents.
  • Unlimited paid time off, 401(k) company matching, disability coverage, FSA, dependent care benefits, and life insurance.
  • Annual bonus and company equity in addition to base salary.
  • Drinks, snacks, and catered team lunches are provided in the offices.

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