Engineer I-Design (ASIC/RTL)

Location: Allentown, Pennsylvania, United States; onsite role. Travel may be required for 0–25% of working time. Applicants must provide proof of US citizenship, permanent US residency, or protected-individual status under US export-control regulations.

Company

A global semiconductor technology organization developing products and solutions for imaging, networking, system connectivity, compute, and data storage.

What you will do

• Design RTL modules, analyze performance, and create detailed design specifications.
• Implement and verify RTL through synthesis, simulation, formal verification, and pre-layout/post-layout timing analysis.
• Develop high-speed design techniques to improve data and command-processing bandwidth, reduce latency, and increase reliability.
• Design complex state machines and datapath logic for SoC hard and soft IP blocks.
• Support design porting to test chips and emulation platforms, including FPGA and board implementations.
• Apply industry standards and collaborate with engineering teams to deliver designs on schedule.

Requirements

• 0–2.5 years of experience in RTL design for ASIC implementation.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Practical knowledge of RTL design, synthesis, formal verification, RTL/gate-level simulation, clock-domain analysis, and static timing analysis.
• Proficiency in SystemVerilog and scripting with TCL, Perl, or Python.
• Experience with Linux, Verilog simulation tools, and writing detailed design specifications.
• Strong analytical, written, oral, presentation, teamwork, and scheduling skills.

Nice to have

• Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• FPGA and ASIC SoC design experience.
• Laboratory experience with system-level validation.

Culture & Benefits

• Employee development and career-growth programs.
• Values-based decision-making and a collaborative engineering community.
• Work is performed 100% indoors, with approximately 80% sitting, 10% standing, and 10% walking.
• Equal opportunity and affirmative-action employment environment.