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Integrated Circuits Intern (Summer 2027)

20 - 45$
Формат работы
onsite
Тип работы
fulltime
Грейд
trainee
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Integrated Circuits Intern (Summer 2027) (ASIC/mixed-signal design): Contributing to integrated-circuit architecture, modeling, simulation, verification, testing, and documentation with an accent on analog/digital tradeoffs and transistor-level design. Focus on designing and simulating circuits with Cadence, MATLAB, Simulink, and System Verilog, developing requirements and test plans, and evaluating hardware-versus-software implementations.

Location: Cambridge, Massachusetts, United States

Salary: $20.00–$45.00 per hour

Company

hirify.global is an independent, nonprofit research and development company delivering engineering solutions for national challenges across defense, space exploration, and biomedical engineering.

What you will do

  • Contribute to integrated-circuit solutions and requirements based on complex customer problems.
  • Design and simulate circuits using functional modeling tools such as MATLAB, Simulink, and System Verilog.
  • Design and simulate transistor-level circuits to implement architectures.
  • Evaluate system-on-chip tradeoffs across analog hardware, digital hardware, and software implementations.
  • Participate in verification planning, bench-level testing, analysis, and test reporting.
  • Develop architectural descriptions, interface definitions, requirements, and other design documentation.

Requirements

  • Enrollment in an accredited full-time undergraduate or graduate degree program.
  • Proficiency with Cadence or equivalent integrated-circuit design tools, such as Virtuoso, Genus, Innovus, Tempus, or Voltus.
  • Strong mathematical, organizational, communication, and time-management skills.
  • Ability to work independently and collaboratively in multidisciplinary engineering teams.
  • Strong computer skills, including Microsoft Word, PowerPoint, and Excel.
  • Applicants may be required to obtain and maintain a government security clearance.

Nice to have

  • Interest or proficiency in mixed-signal modeling and verification tools such as SystemVerilog, SV-RNM, or Verilog-AMS.
  • Scripting experience with Python or SKILL for automating design, implementation, verification, and test flows.

Culture & Benefits

  • Collaborative, multidisciplinary research and development environment.
  • Flexibility regarding working hours and program duration based on school schedule and availability.
  • Workplace flexibility programs, employee clubs, health and finance workshops, off-site social events, and local cultural discounts.
  • Inclusive workplace with equal opportunity and reasonable accommodation support.

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