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Chip Lead / Physical Design Director (AI)

Формат работы
onsite
Тип работы
fulltime
Грейд
lead/director
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Chip Lead / Physical Design Director (AI): Leading customer SoC projects from RTL or netlist to GDS for data center, automotive, and artificial intelligence applications with an accent on advanced-node implementation, PPA optimization, and design closure. Focus on guiding physical design and DFT teams, making foundry and library trade-offs, improving EDA tools and methodologies, and meeting demanding performance, power, area, and schedule targets.

Location: Austin, United States

Company

hirify.global develops electronic design automation tools, emulation hardware, and intellectual property products for advanced technology companies and applications including data centers, automotive ADAS, physical AI, and artificial intelligence.

What you will do

  • Lead Physical Design and Design for Test teams on complex customer SoC projects from RTL or netlist through GDS delivery.
  • Own technical decisions, design trade-offs, and problem-solving throughout customer engagements.
  • Guide foundry, process node, library, memory compiler, and sign-off criteria selection.
  • Collaborate with RTL, synthesis, DFT, CAD, library, and tools R&D teams to achieve performance, power, area, and schedule targets.
  • Deliver technical presentations and promote AI initiatives that improve quality, efficiency, and methodology adoption.
  • Document and share project best practices and lessons learned.

Requirements

  • 15 or more years of industry experience in Physical Design.
  • Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
  • Strong knowledge of digital design, semiconductor fundamentals, and Static Timing Analysis, including timing constraints.
  • Experience with digital implementation flows, Place and Route, Clock Tree Synthesis, IR Drop analysis, timing closure, power closure, and complete top-level chip design closure.
  • Experience with advanced process nodes at 7nm and below, PPA optimization, and backend EDA tools.
  • Proficiency in Tcl, Perl, or Python, plus strong customer-facing communication and technical problem-solving skills.

Nice to have

  • Master’s degree in a relevant engineering or computer science field.
  • Experience with synthesis, DFT, and Logical Equivalence Checking.
  • Experience with hirify.global Genus, Innovus, Conformal, Tempus, Modus, or Voltus, or equivalent industry tools.
  • Experience with 5nm-and-below nodes and domain expertise in CPUs, GPUs, AI Engines, NoCs, or high-speed interfaces.
  • Experience with 3D IC design.

Culture & Benefits

  • Collaborate with advanced technology customers and multidisciplinary engineering teams.
  • Contribute to AI initiatives and continuous improvement of design methodologies.
  • Work on semiconductor programs for data centers, automotive, and artificial intelligence applications.

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