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7 дней назад

Design Manual Publishing & Ground Rule Validation Engineer (2027 New College Graduate)

85 000 - 146 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
trainee
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Design Manual Publishing & Ground Rule Validation Engineer (2027 New College Graduate) (Semiconductor Design Rules/EDA): Developing, validating, documenting, and publishing semiconductor design rules and Design Manual content for manufacturable GlobalFoundries technologies with an accent on silicon characterization, statistical analysis, and PDK release quality. Focus on coordinating ground-rule validation, analyzing design-of-experiment data, and improving documentation publishing workflows.

Location: Essex Junction, Vermont, USA

Salary: $85,000–$146,000 per year

Company

hirify.global manufactures semiconductors and develops technology solutions for high-growth markets.

What you will do

  • Develop, optimize, qualify, document, and publish semiconductor design rules across multiple technology platforms.
  • Perform design-rule margin calculations using process, reliability, yield, and silicon-characterization data.
  • Develop layout-based designs of experiments and electrical test structures for technology test vehicles.
  • Coordinate ground-rule validation from layout creation through silicon measurement and data collection.
  • Analyze silicon characterization results using statistical and data-mining techniques to assess manufacturability.
  • Own Design Manual content, quality reviews, revision control, release documentation, and publishing workflow improvements for PDK releases.

Requirements

  • Graduating with a bachelor's degree in Electrical Engineering, Materials Science, Solid State Physics, or a related field.
  • Minimum overall GPA of 3.0 and good academic standing.
  • English fluency required for written and verbal communication.
  • Understanding of semiconductor fabrication flow, nanofabrication, solid-state and semiconductor-device physics, and design-of-experiments methodology.
  • Strong data analysis, data mining, problem-solving, organizational, and documentation skills.
  • Familiarity with Cadence Virtuoso Schematic Editor, Virtuoso Layout Suite, and Calibre DRC and LVS.

Nice to have

  • Prior related internship or co-op experience.
  • Leadership experience in the workplace, academic projects, or competitions.
  • Interest in using AI tools and emerging technologies to improve productivity and decision-making.
  • Project management skills and the ability to navigate ambiguity.
  • Master's or PhD in a relevant engineering or physics discipline, or semiconductor-industry experience in device engineering, process integration, or unit-process areas.

Culture & Benefits

  • Full-time employment for new college graduates.
  • Accelerated training in a fast-paced work environment.
  • Cross-functional collaboration, mentorship, networking, and leadership opportunities.
  • Opportunities for talent mobility and long-term professional development.
  • Work is performed in support of Environmental, Health, Safety & Security requirements.

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