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6 дней назад

Staff Engineer – Microelectronics Packaging Technology

101 361 - 178 255$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Staff Engineer – Microelectronics Packaging Technology (SiP/ANSYS/SOLIDWORKS): Designing and developing highly integrated System-In-Package and module subsystems for aerospace, defense, industrial, and medical applications with an accent on heterogeneous integration, 3D package design, and physics-based thermal and mechanical analysis. Focus on optimizing package architectures, solving chip-package and package-board reliability challenges, and developing manufacturable packaging technologies from early technology readiness levels through manufacturing readiness.

Location: Syracuse, NY, United States

Salary: $101,361–$178,255 annually, with a possible annual or quarterly company bonus.

Company

hirify.global is a publicly traded US manufacturer of printed circuit boards, RF components, microelectronic assemblies, and mission systems.

What you will do

  • Lead the design and development of advanced System-In-Package and module solutions using 2D/3D packaging, flip-chip interconnects, WLP bumped die, and embedded die.
  • Create and optimize detailed 3D package designs in SOLIDWORKS in collaboration with RF, microwave, and electrical engineering teams.
  • Perform ANSYS-based mechanical, vibration, thermal, and reliability simulations covering chip-package interaction, package-board interaction, warpage, and stress.
  • Develop SiP design infrastructure, including package design flows, 3D modeling and simulation methods, and design rules.
  • Evaluate materials, assembly processes, emerging packaging technologies, and manufacturing risks.
  • Prepare technical proposals, white papers, conference publications, tradeoff analyses, and planning inputs for packaging projects.

Requirements

  • Bachelor’s degree in mechanical engineering with materials coursework; a master’s degree is a plus.
  • At least 9 years of relevant experience, including 6–7 years of hands-on semiconductor packaging development.
  • Advanced 3D modeling skills with SOLIDWORKS and FEA-based mechanical and thermal analysis with ANSYS.
  • Strong knowledge of semiconductor packaging, heterogeneous SiPs, substrates, silicon interconnects, metallurgy, underfills, epoxies, thermal interface materials, shielding, and assembly processes.
  • Ability to solve ambiguous interdisciplinary engineering problems using physics-based models, statistics, design of experiments, and structured tradeoff analysis.
  • Must have a background permitting the US Department of Defense to issue a Secret clearance when required; ITAR-related technical data access is restricted to US citizens and US permanent residents.

Nice to have

  • Master’s education in a relevant engineering discipline.
  • Exposure to basic vibration analysis concepts.

Culture & Benefits

  • Work as an individual contributor within a multidisciplinary advanced technology team.
  • Collaborate with manufacturing, operations, business units, material suppliers, and process vendors.
  • Health, dental, and vision insurance options.
  • 401(k), flexible spending and health savings accounts, life and disability insurance.
  • Paid vacation and holidays; benefits generally begin on the first day of the month following hire.

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