Memory System Designer and Place and Route Engineer

Location: Austin, Texas, United States; onsite

Annual base salary: USD 109,700–175,500, plus discretionary annual bonus and equity awards.

Company

hirify.global develops semiconductor and technology solutions, including large memory blocks and subsystems.

What you will do

• Architect and design memory subsystems.
• Implement subsystem RTL designs using Verilog.
• Perform place and route and other physical design activities.
• Drive design closure across timing, DRC, LVS, and EM/IR requirements.
• Run gate netlist synthesis and logical equivalency checks.

Requirements

• At least 8 years of relevant experience.
• Bachelor’s degree in Electrical Engineering.
• Strong design skills and experience writing and debugging Verilog RTL.
• Expertise with place and route, STA, DRC, EM/IR, synthesis, and design closure tools.
• Programming experience with Python and automation scripting.
• Understanding of memory behavior, logical equivalency checking, and synthesis tools, plus strong communication and leadership skills.

Culture & Benefits

• Medical, dental, and vision insurance.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Employee Assistance Program, paid holidays, paid sick leave, and vacation time.
• Paid family leave and other legally applicable leaves of absence.
• Annual bonus, competitive new-hire equity grants, and annual equity awards.