Назад
Company hidden
8 дней назад

Sr Principal Design Engineer (Mixed-Signal)

154 000 - 286 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Sr Principal Design Engineer (Mixed-Signal): Developing physical IP for industry-standard high-speed serial links across mixed-signal design, verification, and post-silicon testing with an accent on circuit architecture, performance closure, and advanced process technologies. Focus on designing circuits from high-level specifications, creating and executing silicon validation plans, and collaborating with digital teams to resolve functional and performance challenges.

Location: Cary, United States

Annual salary: $154,000–$286,000 in California, plus potential incentive compensation.

Company

hirify.global develops technology for electronic design and supports engineering work on physical IP for high-speed serial links.

What you will do

  • Develop physical IP for industry-standard high-speed serial links.
  • Design and develop mixed-signal circuits from high-level architectural specifications.
  • Contribute to mixed-signal verification, testing, and functional and performance closure.
  • Develop and execute post-silicon test and silicon validation plans.
  • Collaborate with digital engineering teams and contribute to project leadership.

Requirements

  • Thorough understanding of mixed-signal circuit design fundamentals and design verification flows.
  • Experience with the hirify.global analog design environment and basic signal processing concepts.
  • Ph.D. in Electrical Engineering with 5+ years, or an M.S. in Electrical Engineering with 7+ years of mixed-signal design industry experience.
  • Experience must include advanced process technologies.
  • Excellent verbal and written communication skills, with the ability to work independently.

Nice to have

  • Experience with serial-link design techniques, ADCs, DACs, PLLs, DLLs, or CDRs.
  • MATLAB or C experience for architecture development.
  • SystemVerilog or VerilogA experience for functional model development.
  • Perl or Python scripting for automation.
  • Silicon validation testing experience.

Culture & Benefits

  • Opportunity to work on technology intended to solve complex engineering problems.
  • Paid vacation and paid holidays.
  • 401(k) plan with employer match.
  • Employee stock purchase plan.
  • Medical, dental, and vision plan options.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →