Product Architectural Model Development Leader (FPGA)

Location: San Jose, California, United States. Shift 1. Applicants must be eligible for any required U.S. export authorizations.

Salary: $231,500–$341,075 USD annually for the Bay Area, California. Incentive opportunities are also available.

Company

hirify.global develops FPGA products and related architecture, design, verification, and software enablement solutions.

What you will do

• Lead a team developing cycle-approximate and functional models of FPGA fabric, DSP blocks, memory hierarchies, hard IP, transceivers, and NoC.
• Define modeling methodologies, coding standards, and architecture using C++, SystemC, Python, and related simulation technologies.
• Own the model development roadmap from early architecture concepts and pathfinding through RTL freeze.
• Translate architectural specifications and microarchitecture decisions into executable behavioral models used by architecture, verification, RTL, firmware, software, and compiler teams.
• Establish models as golden references for RTL verification, co-simulation, formal checking, performance analysis, and early customer enablement.
• Build simulation infrastructure, regression frameworks, CI pipelines, versioning, documentation, and automation for model validation.

Requirements

• Bachelor’s degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field; a Master’s or PhD is preferred.
• 15+ years of experience in silicon architecture, design, or verification, including 5+ years in a technical leadership role.
• Hands-on experience developing behavioral, functional, or performance models in C++, SystemC, and/or SystemVerilog.
• Deep understanding of FPGA or ASIC architecture, including fabric, memory subsystems, interconnect, and hard IP blocks.
• Experience bridging architecture specifications into simulatable models and using pre-silicon models for software, firmware, driver, or customer development.
• Experience with RTL design and verification flows, model-to-RTL equivalence, and leading technical teams across complex silicon programs.

Nice to have

• FPGA architecture experience involving embedded memory, transceivers, or NoC/interconnect.
• Performance or pathfinding modeling for PPA trade-off studies.
• Spec-to-model or model-to-RTL automation and code-generation experience.
• Formal methods, golden-model verification, or early software/compiler enablement experience.
• Experience delivering customer-consumable pre-silicon models or integrating architectural models into development tools.

Culture & Benefits

• Regular full-time employment.
• Cross-functional collaboration with architecture, verification, RTL design, firmware, software, compiler, tools, and customer-facing engineering organizations.
• Incentive opportunities based on individual and company performance.
• Use of artificial intelligence in applicant screening, assessment, or selection.