ASIC Technical Lead (Neural Recording)

Location: San Diego, California, US

Salary: $180,000–$220,000 per year, plus stock option or restricted stock unit grants.

Company

hirify.global is developing a high-channel-count neural recording ASIC in partnership with an external IC design house.

What you will do

• Author and maintain versioned, traceable ASIC requirements and specifications as the single source of truth for the design partner.
• Run block-level, top-level, and pre-tapeout architecture and design reviews, independently assessing schematics, netlists, and simulation results.
• Review SPICE/Cadence simulations, DRC/LVS results, and DFT plans; own tapeout readiness and go/no-go decisions.
• Manage design risks involving process corners, matching, noise budgets, and power budgets across the full channel count.
• Partner with the AFE Test & Integration Engineer during first-silicon bring-up and lead root-cause analysis of out-of-specification results.
• Lead respin reviews, re-verification planning, engineering change orders, FMEA updates, and next-generation chip specifications.

Requirements

• B.S. or M.S. in Electrical Engineering or equivalent, with a silicon design emphasis.
• 5+ years of ASIC/SoC design and development experience, including at least one complete ASIC cycle from concept to silicon.
• Strong analog or mixed-signal IC design or verification background, including the ability to critique external schematics and simulations.
• Working fluency with SPICE/Cadence-class simulation review, DRC/LVS, and DFT concepts.
• Experience working with an external design partner, foundry, or fab, including specification and delivery oversight.

Nice to have

• Experience in a regulated medical device environment, including design controls, DHF, 510(k), or PMA.
• Experience with implantable-class electronics.

Culture & Benefits

• Opportunity to own the technical delivery of a cutting-edge neural recording chip.
• Stock option or restricted stock unit grants.