Design Verification Engineer (ASIC)

Location: San Jose, California, United States; legal authorization to work in the US is required

Annual base salary: USD 121,900–195,000

Company

hirify.global supplies SoC and embedded IP solutions through its ASIC Product Division.

What you will do

• Develop verification environments for SoC and IP programs using SystemVerilog and UVM.
• Design UVM agents, behavioral models, coverage models, and assertions.
• Develop randomized and directed test cases against specifications.
• Analyze and debug simulation failures and coverage results.
• Verify designs at system and block levels while collaborating with design and verification engineers.

Requirements

• Bachelor’s degree in Electrical and Electronic Engineering, Computer Science, or an equivalent field.
• 8+ years of relevant industry experience.
• Strong experience with ASIC design verification flows, RTL verification methodologies, SystemVerilog, and UVM or OVM.
• Working knowledge of C/C++, Perl, object-oriented verification languages, and scripting.
• Ability to independently debug designs, analyze complex verification trade-offs, and communicate effectively in a team environment.
• Must have legal authorization to work in the United States.

Nice to have

• Experience with hardware design and debugging, C++/SystemC, emulators, or FPGA-based prototyping.
• Familiarity with chip design methodologies and tools.
• Knowledge of CPU, DDR, bus protocol, network protocol, or DSP design.

Culture & Benefits

• Full-time position within a high-performance design team.
• Annual discretionary bonus and new-hire and annual equity awards, subject to plan documents.
• Medical, dental, and vision coverage.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Paid holidays, sick leave, vacation time, and applicable family and other leaves of absence.