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8 дней назад

Tech Lead, Digital Design Engineer (ASIC)

175 500 - 195 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Tech Lead, Digital Design Engineer (ASIC): Developing front-end digital designs and synthesizable RTL for high-performance switch ASICs powering rack-scale AI infrastructure with an accent on microarchitecture, connectivity protocols, and production silicon delivery. Focus on driving blocks from architecture through GDS, closing timing, coordinating verification and DFT, and debugging complex connectivity issues during silicon bring-up.

Location: San Jose, California, United States

Salary: $175,500–$195,000 per year, depending on experience, level, and business need; discretionary bonus, incentives, and benefits may be available.

Company

hirify.global develops rack-scale AI infrastructure through connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and software technologies.

What you will do

  • Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.
  • Develop front-end digital designs for high-performance networking and server connectivity applications.
  • Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.
  • Analyze performance, power, area, and schedule tradeoffs while resolving implementation issues with cross-functional partners.
  • Partner with verification engineers on UVM-based plans, coverage, failure debugging, silicon bring-up, and lab root-cause analysis.
  • Provide technical leadership across multiple workstreams and communicate risks and progress to stakeholders.

Requirements

  • Bachelor’s degree in Electrical Engineering or a related field.
  • 5–8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
  • Hands-on experience with UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.
  • Front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT.
  • Experience owning blocks from architecture through GDS and using Synopsys and/or Cadence design flows.
  • Must be authorized to work in the United States.

Nice to have

  • Master’s degree in Electrical Engineering or a related field.
  • Experience with PCIe or Ethernet switch products.
  • Familiarity with UVM-based verification and coverage-driven debugging.
  • Silicon bring-up and debugging experience in CMOS technologies at 28nm or below.
  • Python or comparable scripting experience and a collaborative, customer-focused approach.

Culture & Benefits

  • Work on connectivity technology for demanding AI workloads and rack-scale infrastructure.
  • Collaborate across design, verification, physical design, systems, and ecosystem partner teams.
  • Potential eligibility for discretionary bonuses, incentives, and benefits.
  • Inclusive environment that encourages applications from people with diverse backgrounds and experiences.

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