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6 часов назад

Hardware Engineer, Architect (AI)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK/US/Denmark +1 еще
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Hardware Engineer, Architect (AI) (Custom AI Silicon): Defining silicon and system microarchitecture for unconventional compute platforms targeting highly efficient LLM and diffusion model inference with an accent on compute tiles, memory hierarchies, and hardware/software co-design. Focus on translating transformer and diffusion workloads into microarchitectural specifications, defending PPA tradeoffs, co-designing the ISA, and validating designs before tapeout.

Location: Silicon Valley, United States; hybrid

Company

hirify.global develops foundational hardware and software for the semiconductor industry, AI infrastructure, and advanced computing systems.

What you will do

  • Define silicon and system microarchitecture for a custom unconventional compute platform targeting LLM and diffusion model inference.
  • Design AI accelerator compute blocks, including processing-element arrays, datapaths, sparsity support, and reduced-precision computation.
  • Translate transformer and diffusion workloads into hardware specifications covering compute tiles, memory hierarchies, and tile interconnects.
  • Build performance models and make full-stack power, performance, and area trade-offs across algorithms, memory, interconnect, and physical design.
  • Co-design the instruction set architecture and programming model with the compiler team.
  • Direct block-level pre-silicon validation with FPGA design engineers and systems architects, and assess AI accelerator research directions.

Requirements

  • Degree in electrical engineering, computer engineering, computer science, or equivalent experience.
  • Substantial experience architecting or microarchitecting high-performance digital systems such as AI accelerators or complex compute engines.
  • Experience translating workload analysis into datapaths, pipeline stages, and area and power estimates.
  • Experience using cycle-accurate or analytical simulation models to guide architecture decisions before RTL implementation.
  • Experience with quantization, reduced-precision inference, microarchitecture specifications, and collaboration with RTL engineers.
  • Proficiency in Python or C++ and familiarity with SystemVerilog or equivalent RTL.

Culture & Benefits

  • Collaborate across hardware, compiler, RTL, analog, FPGA, systems, and research teams.
  • Work in an environment where the architecture is actively discovered alongside implementation.
  • Participate in research-adjacent work, including reading and potentially publishing research.
  • Inclusive equal-opportunity workplace with reasonable accessibility accommodations.

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