Hardware ASIC Architect (AI Accelerators)

Location: Silicon Valley, United States; hybrid work format

Salary: $200,000–$400,000 per year

Company

hirify.global is an applied AI company developing foundational hardware and software for the semiconductor industry, AI infrastructure, and advanced computing systems in partnership with research institutions.

What you will do

• Define the silicon and system microarchitecture for a custom unconventional compute platform targeting LLM and diffusion model inference.
• Design AI accelerator compute blocks, including processing-element arrays, datapaths, sparsity support, and reduced-precision computation.
• Translate workload analysis and research findings into detailed hardware and microarchitecture specifications for RTL implementation.
• Evaluate performance, power, and area trade-offs across algorithms, memory hierarchies, interconnects, and physical design constraints.
• Co-design the instruction set architecture and programming model with compiler engineers.
• Direct block-level pre-silicon validation using appropriate simulation and prototyping platforms, including FPGA-based validation before tapeout.

Requirements

• Degree in electrical engineering, computer engineering, computer science, or equivalent experience.
• Substantial architecture or microarchitecture experience with high-performance digital systems such as AI accelerators or complex compute engines.
• Ability to translate algorithm-level workload behavior into datapaths, pipeline stages, and area or power estimates.
• Experience with cycle-accurate or analytical simulation models for architecture decisions before RTL implementation.
• Knowledge of quantization and reduced-precision inference techniques, plus experience writing microarchitecture specifications and working with RTL engineers.
• Proficiency in Python or C++ for performance modeling and familiarity with SystemVerilog or equivalent RTL.

Nice to have

• PhD in electrical engineering, computer engineering, computer science, or a related field.
• Research fluency in AI accelerator architecture, including the ability to read or publish relevant research.

Culture & Benefits

• Collaborative work across hardware, compiler, RTL, analog, FPGA, systems, and research teams.
• Opportunity to work on architecture that is actively being discovered alongside implementation.
• Inclusive environment with equal employment opportunity and reasonable accessibility accommodations.