Package Design, Signal and Power Integrity Senior Staff Engineer (Semiconductor Packaging)

Location: Santa Clara, California, United States

Expected base pay: $141,150–$211,400 per year, plus eligibility for bonus and equity plans.

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, carrier, connectivity, and compute infrastructure.

What you will do

• Design, model, and characterize high-speed IC package interconnects for semiconductor products supporting 448 Gb/s data rates and beyond.
• Develop power delivery, signal integrity, and power integrity simulation methodologies and correlate results with laboratory measurements.
• Explore custom high-speed interfaces and new interconnect architectures where established methodologies may not exist.
• Develop package design rules and practical solutions in collaboration with assembly, physical layout, analog, digital, and marketing teams.
• Investigate channel and power delivery network behavior, identify root causes, and drive designs from architecture through implementation and validation.

Requirements

• MS or PhD in Electrical Engineering or Computer Engineering with relevant industry experience.
• Strong understanding of transmission line theory, electromagnetic fundamentals, and frequency- and time-domain analysis.
• Demonstrated ability to independently solve complex signal integrity and power integrity problems.
• Experience with 2-D and 3-D electromagnetic simulation tools such as Ansys HFSS, SI-Wave, and Cadence Clarity, plus power plane analysis tools such as PowerSI or Siwave.
• Working knowledge of channel and circuit simulators such as ADS and HSPICE, laboratory equipment including VNA and TDR, and layout tools such as Allegro, APD, or PADS.
• Strong communication, presentation, documentation, and cross-functional collaboration skills.

Nice to have

• Experience with packaging technologies, package materials, substrate design rules, assembly rules, thermal and mechanical analysis, and digital or analog IC packaging.
• Experience with 2.5D/3D package development and CPC/CPO connectors.
• Ability to automate signal integrity, power integrity, and packaging activities using Python or other scripting tools.
• Experience managing package development across assembly, IC physical layout, analog, digital, and marketing functions.

Culture & Benefits

• Employee stock purchase plan with a two-year lookback.
• New-hire equity grant, annual equity refreshers, and bonus eligibility.
• Family support programs and mental and physical health resources.
• Recognition and service awards.
• Access to export-controlled technology may require an export license review under U.S. regulations.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills in real time.
• AI tools, transcription apps, automated note-taking bots, and real-time answer generators are not permitted during interviews.