Principal Verification Engineer (ASIC)

Location: Aliso Viejo, California, United States; on-site

Company

Jariet Technologies, a hirify.global subsidiary, develops CMOS-based digital communications technologies for micro/mm-wave speeds, beamforming systems, wireless infrastructure, microwave links, and radar applications.

What you will do

• Design and implement verification testbench infrastructure and test cases for system-, chip-, and block-level verification.
• Develop verification methodologies for complex, high-speed digital communication SoCs.
• Implement pseudo-random and functional coverage verification methodologies.
• Create functional test and verification plans.
• Collaborate with the VLSI Design team on verification strategies.
• May lead verification teams or projects.

Requirements

• At least 10 years of relevant experience with a BS degree in Computer Science, Electrical Engineering, Computer Engineering, or a related discipline, or at least 8 years with a Master's degree.
• Strong knowledge of SystemVerilog and class libraries such as UVM, OVM, or VMM.
• Experience with pseudo-random and functional coverage verification methodologies.
• Experience with SVA, PSL, or OVL assertions.
• Excellent written and verbal communication skills.
• Must be a U.S. citizen, lawful permanent resident, conditional resident, asylee, refugee, or otherwise eligible to obtain the required U.S. government authorizations under space technology export regulations.

Nice to have

• Experience with formal model-checking tools such as Cadence IFV or Jasper.
• Experience with DSP and digital communications.

Culture & Benefits

• Collaborative, energetic, and forward-thinking engineering environment.
• Work on leading-edge verification for high-speed digital communication SoCs.
• Opportunity to contribute to emerging beamforming, wireless infrastructure, microwave, and radar technologies.