Principal Design Engineer (ASIC Verification)

Location: Austin, United States

Company

hirify.global develops technology solutions and delivers semiconductor and ASIC project work.

What you will do

• Define verification strategies, methodologies, tools, infrastructure, and project sign-off criteria.
• Design scalable and reusable verification environments with BFMs, monitors, scoreboards, and checkers.
• Lead design verification execution for small to mid-sized customer ASIC projects and translate requirements into execution plans.
• Develop complex tests, sequences, and constrained-random stimulus to achieve high functional coverage.
• Lead root-cause analysis of design bugs and collaborate with design, architecture, and emulation teams.
• Manage coverage analysis, gate-level simulations, project risks, timelines, and technical approval for verification completion.

Requirements

• B.E./B.Tech, M.Tech, or M.S. in Electronics, VLSI, or a related field.
• 8–10 years of hands-on design verification experience in semiconductor, ASIC, or SoC companies.
• Deep expertise in SystemVerilog and UVM, with strong digital design fundamentals covering RTL, timing, clocking, and resets.
• Experience with Xcelium, VCS, Questa, formal verification tools, waveform analysis, and coverage-driven verification.
• Experience with bus protocols such as AXI, AHB, APB, PCIe, or DDR.
• Familiarity with UPF/CPF, low-power verification, gate-level simulation, and power-aware gate-level simulation.

Culture & Benefits

• Leadership and mentorship responsibilities across verification and engineering teams.
• Cross-functional collaboration with design, architecture, and emulation teams.
• Technical ownership of customer projects and verification sign-off.
• Work focused on solving complex technology and semiconductor challenges.