Lead Design Engineer (ASIC/SoC Verification)

Location: Austin, United States

Company

hirify.global develops technology solutions for the semiconductor and electronic design industry.

What you will do

• Define verification strategies, methodologies, tools, and infrastructure, typically using UVM and SystemVerilog.
• Design scalable verification environments with bus functional models, monitors, scoreboards, and checkers.
• Develop complex test cases, sequences, and constrained-random stimulus to achieve high functional coverage.
• Lead root-cause analysis of design bugs and collaborate with design engineers on fixes.
• Use formal verification and gate-level simulation to identify deep bugs and validate timing and reset behavior.
• Manage coverage metrics, verification risks, schedules, and final technical sign-off.

Requirements

• B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or a related field.
• 4–7 years of hands-on design verification experience.
• Experience in semiconductor, ASIC, or SoC companies.
• Experience with UVM/SystemVerilog, functional and code coverage, constrained-random testing, formal verification, and gate-level simulation.
• Ability to mentor junior engineers and collaborate with design, architecture, and emulation teams.

Culture & Benefits

• Full-time employment.
• Leadership and innovation are emphasized, with work focused on solving complex technology problems.